CPA-DA-T: Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability through Asynchrony

[摘要]sf提案#0811504，CPA-DA-T: ？易于编程的大规模并行片上系统的设计和工具：通过异步获得可扩展性？PI: S. Nowick教授（哥伦比亚大学），合作PI: U. Vishkin教授（马里兰大学）联系人：Steven Nowick（哥伦比亚大学）？nowick@cs.columbia.eduJune 2008.30虽然目前的现实是，未来的处理器将会是什么样子还没有定论，但可以肯定的是，它将是并行的。所有主要的商业处理器供应商现在都致力于增加单个芯片上的处理器（即“核”）的数量。然而，现有的同步设计方法存在功耗、性能和可扩展性方面的主要障碍。本建议的重点是一个特定的现有的易于编程和易于教学的多核体系结构。然后，它将连接多个核心和存储器的互连网络确定为实现更低总体功耗的关键瓶颈。目标是通过设计和制造高速异步通信网格，大幅提高系统的功率、鲁棒性和可扩展性。由此产生的并行架构将是全局异步的，局部同步的（即gals风格），它优雅地适应以任意不相关的时钟速率运行的同步内核和存储器，同时提供对时序可变性的鲁棒性和对“即插即用”的支持。（即可扩展的）系统设计。与大多数以前的GALS体系结构不同，这种体系结构在复杂的流水线拓扑结构中将具有显著的性能和功耗要求。此外，将开发计算机辅助设计（即CAD）工具来支持这种新网格的设计，以及应用于整个并行架构的仿真、时序验证和性能分析工具。这项工作将与肯·史蒂文斯教授（犹他大学）的一项单独的NSF CPA提案合作进行。这两个提案将被链接到一个更大的框架中：犹他州小组将协调提供和完善他们基于商业的物理设计工具的开发和支持，而哥伦比亚/马里兰小组将为他们的异步工具应用程序提供一个新的实质性测试用例。预计这项工作将产生广泛的影响。首先，虽然它针对的是一个并行体系结构，但其他几个体系结构将从这项工作中受益，因为互连网络也可以应用于它们。其次，这项工作有望证明异步设计在复杂高性能系统中的好处和作用。最后，这项工作的结果可能使该领域目前正在经历的从串行到并行的范式转变迈出一步；由此产生的首台部分异步高端大规模并行片上计算机可以将可伸缩性水平推向目前可能的水平，并在支持计算机科学和工程中的许多并行应用方面产生广泛影响。

AbstractNSF Proposal #0811504, CPA-DA-T: ?Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability Through Asynchrony? PI: Prof. S. Nowick (Columbia University), co-PI: Prof. U. Vishkin (U. of Maryland)Contact: Steven Nowick (Columbia University) ? nowick@cs.columbia.eduJune 30, 2008While the current reality is that the jury is still out on how the processor-of-the-future will look, one clear certainty is that it will be parallel. All major commercial processor vendors are now committed to increasing the number of processors (i.e. ?cores?) that fit on a single chip. However, there are major obstacles of power consumption, performance and scalability in existing synchronous design methodologies. This proposal focuses on a particular existing easy-to-program and easy-to-teach multi-core architecture. It then identifies the interconnection network, connecting multiples cores and memories, as the critical bottleneck to achieving lower overall power consumption. The target is to substantially improve the power, robustness and scalability of the system by designing and fabricating a high-speed asynchronous communication mesh. The resulting parallel architecture will be globally-asynchronous locally-synchronous (i.e. GALS-style), that gracefully accommodates synchronous cores and memories operating at arbitrary unrelated clock rates, while providing robustness to timing variability and support for ?plug-and-play? (i.e. scalable) system design. Unlike most prior GALS architectures, this one will have significant performance and power requirements in a complex pipelined topology. In addition, computer-aided design (i.e. CAD) tools will be developed to support the design of this new mesh, as well as simulation, timing verification and performance analysis tools to be applied to the entire parallel architecture. This work will be performed in collaboration with a separate NSF CPA proposal under Prof. Ken Stevens (University of Utah). The two proposals will be linked together into a larger framework: the Utah group will coordinate to provide and refine their commercial-based physical design tool development and support, while the Columbia/Maryland group will provide a new substantial test case for their asynchronous tool applications.The work is expected to have broad impact. First, while it is targeted to one parallel architecture, several other architectures will benefit from this work, since the interconnection network can be applied to them as well. Second, the work is expected to demonstrate the benefits and role of asynchronous design for complex high-performance systems. Finally, the outcome of the work could make a step in the paradigm shift from serial to parallel that the field is now undergoing; the resulting first-of-its-kind partly-asynchronous high-end massively-parallel on-chip computer could push the level of scalability beyond what it currently possible and have a broad impact in supporting parallel applications in much of computer science and engineering.