CPA-DA-T: Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability through Asynchrony

摘要NSF提案#0811504，CPA-DA-T：？易于编程的大规模并行片上系统的设计和工具：通过异步获得可扩展性？主要研究者：S. Nowick（哥伦比亚大学），共同主要研究者：U. Vishkin（U.联系人：Steven Nowick（哥伦比亚大学）？nowick@cs.哥伦比亚. edu 2008年6月30日虽然目前的现实是，陪审团仍然对未来的处理器将是什么样子，一个明确的确定是，它将是平行的。 所有主要的商业处理器供应商现在都致力于增加处理器的数量（即？核心？）一个芯片就能装得下 然而，在现有的同步设计方法中，存在功耗、性能和可扩展性的主要障碍。 该提案侧重于一个特定的现有的易于编程和易于教学的多核架构。 然后，它确定了互连网络，连接多个核心和存储器，作为实现更低的整体功耗的关键瓶颈。我们的目标是通过设计和制造一个高速异步通信网，大大提高了系统的功率，鲁棒性和可扩展性。 由此产生的并行架构将是全球异步本地同步（即GALS风格），优雅地容纳在任意不相关的时钟速率操作的同步核心和存储器，同时提供鲁棒性的定时变化和支持？即插即用(i.e.可扩展的）系统设计。 与大多数先前的GALS架构不同，这一架构将在复杂的流水线拓扑中具有显著的性能和功耗要求。此外，将开发计算机辅助设计（即CAD）工具，以支持这种新网格的设计，以及将应用于整个并行架构的模拟，时序验证和性能分析工具。 这项工作将与Ken Stevens教授（犹他州大学）单独的NSF CPA提案合作进行。 这两个提案将被连接到一个更大的框架中：犹他州小组将协调提供和完善他们基于商业的物理设计工具开发和支持，而哥伦比亚/马里兰州小组将为他们的异步工具应用提供一个新的实质性测试案例。这项工作预计将产生广泛的影响。 首先，虽然它是针对一个并行架构，其他几个架构将受益于这项工作，因为互连网络也可以应用于他们。 其次，这项工作预计将证明异步设计的好处和复杂的高性能系统的作用。 最后，这项工作的成果可能会在该领域正在经历的从串行到并行的范式转变中迈出一步;由此产生的第一台部分异步高端并行片上计算机可能会将可扩展性提升到目前可能的水平，并对支持大部分计算机科学和工程中的并行应用产生广泛影响。

AbstractNSF Proposal #0811504, CPA-DA-T: ?Design and Tools for Easy-to-Program Massively Parallel On-Chip Systems: Deriving Scalability Through Asynchrony? PI: Prof. S. Nowick (Columbia University), co-PI: Prof. U. Vishkin (U. of Maryland)Contact: Steven Nowick (Columbia University) ? nowick@cs.columbia.eduJune 30, 2008While the current reality is that the jury is still out on how the processor-of-the-future will look, one clear certainty is that it will be parallel. All major commercial processor vendors are now committed to increasing the number of processors (i.e. ?cores?) that fit on a single chip. However, there are major obstacles of power consumption, performance and scalability in existing synchronous design methodologies. This proposal focuses on a particular existing easy-to-program and easy-to-teach multi-core architecture. It then identifies the interconnection network, connecting multiples cores and memories, as the critical bottleneck to achieving lower overall power consumption. The target is to substantially improve the power, robustness and scalability of the system by designing and fabricating a high-speed asynchronous communication mesh. The resulting parallel architecture will be globally-asynchronous locally-synchronous (i.e. GALS-style), that gracefully accommodates synchronous cores and memories operating at arbitrary unrelated clock rates, while providing robustness to timing variability and support for ?plug-and-play? (i.e. scalable) system design. Unlike most prior GALS architectures, this one will have significant performance and power requirements in a complex pipelined topology. In addition, computer-aided design (i.e. CAD) tools will be developed to support the design of this new mesh, as well as simulation, timing verification and performance analysis tools to be applied to the entire parallel architecture. This work will be performed in collaboration with a separate NSF CPA proposal under Prof. Ken Stevens (University of Utah). The two proposals will be linked together into a larger framework: the Utah group will coordinate to provide and refine their commercial-based physical design tool development and support, while the Columbia/Maryland group will provide a new substantial test case for their asynchronous tool applications.The work is expected to have broad impact. First, while it is targeted to one parallel architecture, several other architectures will benefit from this work, since the interconnection network can be applied to them as well. Second, the work is expected to demonstrate the benefits and role of asynchronous design for complex high-performance systems. Finally, the outcome of the work could make a step in the paradigm shift from serial to parallel that the field is now undergoing; the resulting first-of-its-kind partly-asynchronous high-end massively-parallel on-chip computer could push the level of scalability beyond what it currently possible and have a broad impact in supporting parallel applications in much of computer science and engineering.