Kinetics of Ultra-Thin Metal Oxide and Silicate Film Deposition on Silicon

金属/氧化物/半导体晶体管的栅极长度持续缩小到100纳米以下，将需要具有更高介电常数的新型金属氧化物栅极绝缘体，以保持大电容（即相当于1nm的SiO2）并最小化栅极隧穿电流。金属氧化物在硅上的典型低温化学气相沉积（CVD）工艺会在硅/金属氧化物界面处形成一层不需要的薄（1至2 nm） SiO2或金属硅酸盐层。界面结构是由有利于消耗硅衬底的单个沉积反应步骤的动力学决定的，即使沉积的大块氧化物在硅上是热力学稳定的，这表明在原生SiO2/Si体系中没有遇到的非原生金属氧化物/硅界面问题。具体来说，如何控制非原生介电沉积在硅上的前几埃，以达到界面上所需的键结构、成分和电子质量？这个问题延伸到其他异质结应用，如光学互连，磁阻器件，生物功能系统等，其中界面结构的原子尺度控制对器件性能很重要。在这个项目中，将研究氧化钇、硅酸钇和其他金属氧化物在硅上沉积时界面层形成的动力学。这将包括对衬底消耗和界面氧化物形成的表面处理的研究，以及硅/氧化钇和硅/硅酸钇界面的电性能。这项工作将包括直接测量等离子体和热CVD中的沉积反应动力学，使用原位红外光谱和在线俄歇电子能谱。该项目将与哈佛大学的Roy Gordon合作完成，他将提供各种反应物，以确定金属-有机前驱体结构对界面反应的影响。原子层沉积方法将用于演示控制界面的突然性和改进的电子性能。这些实验将有助于建立表面反应、工艺温度和沉积薄膜电介质的电性能之间的新联系，并将对控制其他亚纳米电子、光学和磁性器件的界面结构产生影响。

Abstract - Parsons - 0072784Continued scaling of metal/oxide/semiconductor transistors to sub-100 nm gate lengths will require new metal oxide gate insulators with higher dielectric constants to maintain large capacitances (i.e., equivalent to 1nm of SiO2) and minimize gate tunneling currents. Typical low temperature chemical vapor deposition (CVD) processes for metal oxides on silicon result in an unwanted thin (1 to 2 nm) SiO2 or metal silicate layer at the Si/metal oxide interface. The interface structure is determined by the kinetics of individual deposition reaction steps that favor consumption of the silicon substrate, even when the deposited bulk oxide is thermodynamically stable on silicon which indicates a problem for non-native metal oxide/silicon interfaces not encountered in the native SiO2/Si system. Specifically, how does one control the first few angstroms of non-native dielectric deposition on silicon to achieve the required bond structure, composition, and electronic quality at the interface? This problem extends to other heterojunction applications, such as optical interconnects, magnetoresistive devices, bio-functional systems, etc., where atomic-scale control of interface structure is important for device performance. In this project the kinetics of interface layer formation during deposition of yttrium oxide, yttrium silicate, and other metal oxides on silicon will be studied. This will include studies of surface treatment on substrate consumption and interface oxide formation, and electrical performance of silicon/yttrium oxide and silicon/yttrium silicate interfaces.The work will involve direct measurement of deposition reaction kinetics in plasma and thermal CVD, using in-situ infrared spectroscopy and on-line Auger electron spectroscopy. The project will be done in collaboration with Roy Gordon at Harvard University, who will provide various reactants, to determine the effect of metal-organic precursor structure on interface reactions. Atomic layer deposition methods will be used to demonstrate controlled interface abruptness and improved electronic performance. These experiments will help establish new links between surface reactions, process temperature, and electrical performance of deposited thin film dielectrics, and will have implications for controlling interface structures in other sub-nm electronic, optical, and magnetic devices.