Kinetics of Ultra-Thin Metal Oxide and Silicate Film Deposition on Silicon

摘要 - Parsons - 0072784 金属/氧化物/半导体晶体管的栅极长度持续缩小至 100 nm 以下，将需要具有更高介电常数的新型金属氧化物栅极绝缘体，以维持大电容（即相当于 1 nm 的 SiO2）并最大限度地减少栅极隧道电流。 硅上金属氧化物的典型低温化学气相沉积 (CVD) 工艺会在硅/金属氧化物界面处产生不需要的薄层（1 至 2 nm）SiO2 或金属硅酸盐层。 界面结构由有利于硅衬底消耗的各个沉积反应步骤的动力学决定，即使沉积的块状氧化物在硅上是热力学稳定的，这表明在天然SiO2/Si系统中未遇到非天然金属氧化物/硅界面的问题。 具体来说，如何控制硅上非天然电介质沉积的前几埃，以在界面处实现所需的键合结构、成分和电子质量？ 这个问题延伸到其他异质结应用，例如光学互连、磁阻器件、生物功能系统等，其中界面结构的原子级控制对于器件性能非常重要。 在该项目中，将研究氧化钇、硅酸钇和其他金属氧化物在硅上沉积过程中界面层形成的动力学。 这将包括对基材消耗和界面氧化物形成的表面处理以及硅/氧化钇和硅/硅酸钇界面的电性能的研究。这项工作将涉及使用原位红外光谱和在线俄歇电子能谱直接测量等离子体和热CVD中的沉积反应动力学。 该项目将与哈佛大学的罗伊·戈登合作完成，后者将提供各种反应物，以确定金属有机前体结构对界面反应的影响。 原子层沉积方法将用于演示受控的界面突变和改进的电子性能。 这些实验将有助于在沉积薄膜电介质的表面反应、工艺温度和电性能之间建立新的联系，并对控制其他亚纳米电子、光学和磁性器件中的界面结构产生影响。

Abstract - Parsons - 0072784Continued scaling of metal/oxide/semiconductor transistors to sub-100 nm gate lengths will require new metal oxide gate insulators with higher dielectric constants to maintain large capacitances (i.e., equivalent to 1nm of SiO2) and minimize gate tunneling currents. Typical low temperature chemical vapor deposition (CVD) processes for metal oxides on silicon result in an unwanted thin (1 to 2 nm) SiO2 or metal silicate layer at the Si/metal oxide interface. The interface structure is determined by the kinetics of individual deposition reaction steps that favor consumption of the silicon substrate, even when the deposited bulk oxide is thermodynamically stable on silicon which indicates a problem for non-native metal oxide/silicon interfaces not encountered in the native SiO2/Si system. Specifically, how does one control the first few angstroms of non-native dielectric deposition on silicon to achieve the required bond structure, composition, and electronic quality at the interface? This problem extends to other heterojunction applications, such as optical interconnects, magnetoresistive devices, bio-functional systems, etc., where atomic-scale control of interface structure is important for device performance. In this project the kinetics of interface layer formation during deposition of yttrium oxide, yttrium silicate, and other metal oxides on silicon will be studied. This will include studies of surface treatment on substrate consumption and interface oxide formation, and electrical performance of silicon/yttrium oxide and silicon/yttrium silicate interfaces.The work will involve direct measurement of deposition reaction kinetics in plasma and thermal CVD, using in-situ infrared spectroscopy and on-line Auger electron spectroscopy. The project will be done in collaboration with Roy Gordon at Harvard University, who will provide various reactants, to determine the effect of metal-organic precursor structure on interface reactions. Atomic layer deposition methods will be used to demonstrate controlled interface abruptness and improved electronic performance. These experiments will help establish new links between surface reactions, process temperature, and electrical performance of deposited thin film dielectrics, and will have implications for controlling interface structures in other sub-nm electronic, optical, and magnetic devices.