Engineered Nanoparticle Electronic and Photonic Device Materials

这项提案是应“纳米科学与工程”(NSF 00-119)的征集而提交的。我们提出了一项加州理工大学/NASA-JPL/Agere Systems的联合研究计划，以开发用于硅纳米晶非易失性存储器和相关纳米级电子器件的新材料。根据该计划：将开发新的基于气溶胶的硅纳米颗粒和纳米线工程方法，以实现形成纳米颗粒和纳米线阵列，并精确控制颗粒尺寸、颗粒数量和阵列结构。这些方法将与硅超大规模集成电路(ULSI)电路工艺技术兼容。o气溶胶合成和胶体处理的硅纳米颗粒和纳米线阵列将以最先进的器件尺寸集成到硅基金属氧化物半导体(MOS)器件中，从而产生纳米级存储器件。o将开发介质异质结层状隧道势垒，以实现同时进行超快充电注入和极长的电荷保持时间，我们将研究通过电注入和光激载流子注入的纳米晶充电，以评估分层隧道势垒性能，并确定是否可以利用量子尺寸对电子态密度的影响来控制电子充电能量。工作的重点是最近展示的高性能气溶胶硅纳米晶存储器件，该器件是由目前的纳米级跨学科研究小组在先前NSF的支持下开发的。硅纳米颗粒包括作为纳米晶体非易失性存储器的存储节点的浮动栅极。气溶胶合成可以控制硅纳米晶的大小和形状，这是其他合成方法难以实现的。独一无二的是，我们的团队成功地将气相合成的气溶胶纳米颗粒集成到高性能硅基电子器件中，该电子器件以0.18微米的设计规则在200 mm基板上通过超清洁工艺在Au器件尺寸下制造。对晶体管亚阈值和导通性能、保持时间、编程擦除循环、栅极和漏极干扰特性的广泛电学表征表明，这些器件是高性能存储器件。Caltech/JPL/Agere NIRT团队的不同寻常之处在于，他们结合了Caltech开发的新电子材料的基础研究，然后将材料直接集成到灵活的、最先进的硅器件工艺中，该工艺在Caltech和Agere系统的制造设施中进行。

This proposal was submitted in response to the solicitation "Nanoscale Science and Engineering" (NSF 00-119). We propose a joint Caltech/NASA-JPL/Agere Systems research program to develop new materials for Si nanocrystal nonvolatile memories and related nanoscale electronic devices. Under the program:o New aerosol-based Si nanoparticle and nanowire engineering methods will be developed to enable formation nanoparticle and nanowire arrays with precise control of particle size, particle number and array structure. These methods 'will be compatible with Si ultralarge scale integrated (ULSI) circuit process technology.o Aerosol-synthesized and colloidally processed silicon nanoparticle and nanowire arrays with novel configurations will be integrated into Si-based metal-oxide-semiconductor (MOS) devices at state-of-the-art device dimensions yielding nanometer-scale memory devices.o A dielectric heterostructure layered tunnel barrier will be developed to achieve simultaneous ultrafast chargc injection and extremely long charge retention times, which are mutually exclusive for existing conventional dielectric tunnel baffler designs.o Nanocrystal charging via electrical injection and photoexcited carrier injection will be studied to assess layered tunnel barrier performance and to determine whether quantum size effects on the density of electronic states can be exploited for control of electronic charging energy.The focal point of the work is a recently demonstrated high-performance aerosol silicon nanocrystal memory device, developed by the present nanoscale interdisciplinary research (NIRT) team under prior NSF support. Silicon nanoparticles comprise the floating gate that is the storage node of a nanocrystal nonvolatile memory. Aerosol synthesis allows control of Si nanocrystal size and shape that are difficult to achieve by other synthesis methods. Uniquely, our team has successfully integrated vapor-synthesized aerosol nanoparticles into a high-performance silicon-based electronic device, fabricated at 0.18 micron design rules on 200 mm substrates by ultraclean processing at state-of-the-au device dimensions. Extensive electrical characterization of transistor subthreshold and turn-on performance, retention time, program-erase cycling, gate and drain disturb characteristics indicated that these devices are high performance memory devices. The Caltech/JPL/Agere NIRT team is unusual in its combination of basic research on new electronic materials developed at Caltech followed by direct materials integration into a flexible, state-of-the-au silicon device process carried out at Caltech and Agere System's fabrication facilities.