Design and Synthesis of Power Efficient Programmable Fabric

集成电路(IC)制造成本的快速增长以及设计生产率和制造能力之间不断扩大的差距可能会阻碍IC技术按照摩尔定律继续进步。可编程器件提供了一种极具吸引力的解决方案，可显著降低单位摊销制造成本，并通过在各种应用中重复使用相同的硅实现来显著提高设计生产率。然而，现有的可编程电路和体系结构不是高能效的。在某些情况下，与定制IC设计相比，它们的功耗可能会高出100倍。该项目专注于研究和开发高能效的可编程电路结构和体系结构以及相关的综合工具，旨在将功耗降低10倍以上。我们的研究将遵循两个关键原则：(I)使用高度定量的方法进行电路和架构设计和优化；(Ii)整合从电路级到结构级和系统级的不同级别的优化技术，最后是综合工具，以开发具有最高功率效率的新型可编程器件。这项研究的成果包括：(1)灵活的功耗评估框架，以实现对可编程逻辑器件的准确定量评估；(2)新的电路和结构，以减少可编程器件中的泄漏和动态功耗；(3)用于动态电源管理的时钟门控和功率门控的新实现；以及(4)有效和高效的算法和工具，以支持上述电路级、结构级和系统级的优化技术。该项目的广泛影响包括：(1)研究成果的及时传播和技术转让，以使可编程器件的新应用能够显著地惠及整个信息技术(IT)行业；(2)让研究生和可能的本科生参与建议的研究，并把最新的研究方法/结果纳入教学，这将有助于培训未来的研究人员和工程师，使其能够进一步发展信息技术。

Rapid increase of manufacturing costs of the integrated circuit (IC) and the widening gap between the design productivity and manufacturing capacity may prevent the IC technology from continuing to advance according to the Moore's Law. Programmable devices offer an attractive solution for significantly lowering the amortized manufacturing cost per unit and dramatically improving the design productivity through re-use of the same silicon implementation for a wide range of applications. However, existing programmable circuits and architectures are not power efficient. In some cases, they may consume 100x higher power compared to customized IC designs. This project focuses on research and development of power-efficient programmable circuit fabrics and architectures and associated synthesis tools, and is aimed to reduce the power dissipation by over 10x. Our research will be guided by two key principles: (i) the use of a highly quantitative approach to circuit and architecture design and optimization; (ii) the integration of different levels of optimization techniques, from circuit-level to fabric-level and system-level, and finally synthesis tools, for developing novel programmable devices with the highest power efficiency. Outcome of this research includes: (1) A flexible power evaluation framework to enable accurate quantitative evaluation of programmable logic devices; (2) Novel circuits and fabrics to reduce leakage and dynamic power in programmable devices; (3) Novel implementation of clock gating and power gating for dynamic power management; and (4) effective and efficient algorithms and tools to support the aforementioned circuit-level, fabric-level, and system-level optimization techniques.Broader impacts of this project include (1) Timely dissemination of research results and technology transfer to enable new applications of programmable devices that can significantly benefit the overall information technology (IT) industry; (2) Involvement of graduate and possibly undergraduate students in the proposed research and include the latest research methodologies/results into teaching, which will help to train future researchers and engineers for further advancement of the information technology.