CPA: Closing the Gap in VLSI Physical Design

提案编号：0430077INSTUTION：加州大学洛杉矶分校PRINCIPAL研究员：Cong，Jason TITLE：CPA：弥合VLSI物理设计的差距摘要：Gordon Moore的著名观察，即每个集成电路的晶体管数量每两年翻一番，在过去的40年里一直是正确的。这种爆炸性增长的影响几乎已经改变了社会的所有领域，使最近信息技术领域的所有革命成为可能：个人计算、电信、生物信息学、数字成像、电子商务等。随着阻碍硅基电路密度持续增加的最终经济和物理障碍开始形成，自动化设计工具在决定系统性能方面发挥着越来越重要的作用。最近的研究表明，在从实际工业测试案例改编的简化电路基准上，现有的电路布局工具远远不是最优的(超过70%-150%的有线长度)。如果这一质量差距能够缩小，由此产生的好处将相当于将制造工艺技术向前推进几代，如果可行，其成本通常以数十亿美元来衡量。这项研究的目标是为VLSI物理设计开发新的、可扩展的算法，以便在存在复杂的时间和温度约束的情况下，通过三维设计优化实现多代摩尔定律的性能改进。本项目的重点将主要放在电路布局上，因为这是最限制互连布线布局的步骤，而互连布线布局是决定系统性能的关键。核心布局问题是将所有电路元件布置在给定的矩形内，使得它们中没有两个重叠，并且使得总有线长度的标准估计最小化。通过对现有算法偏离最优性的更广泛和更深入的分析，以及这种偏差如何随着设计规模的增加而变化，将被用来为核心布局模型问题开发一个高效和优化的布局引擎。引擎的可伸缩性将源自多尺度框架，在该框架中，目标和约束在分辨率尺度的层次结构中同时被表示和操纵。然后，该引擎将被扩充以处理2-D和3-D设置中的各种复杂约束，例如信号传播时间、最大布线密度、最高温度和大小变化很大的电路元件。以几乎可以忽略的成本推进相当于整个技术生成的更广泛的影响将是相当大的。随着以前难以解决的问题逐渐变得可以解决，原始计算能力的大幅跃升最终转化为新的定性理解。此外，潜在的更大影响是，通过将详细的物理模型整合到一个可扩展的程序中，以优化数百万个相互关联的元素，可能在基础科学方面取得进展。最终，纳米级设计问题的巨大规模和复杂性只有通过尚未开发的可扩展算法才能现实地解决。对于物理上真实的VLSI设计来说，成功地制定一种真正可扩展的方法有望对未来的设计范例产生持久而深远的影响。

PROPOSAL NO: 0430077INSTITUTION: University of California-Los AngelesPRINCIPAL INVESTIGATOR: Cong, JasonTITLE: CPA: Closing the Gap in VLSI Physical DesignAbstract:Gordon Moore's famous observation that the number of transistors per integrated circuit doubles every two years has held true for the last four decades. The impact of this explosive increase has already transformed practically all areas of society, making possible all the recent revolutions in information technology: personal computing, telecommunications, bioinformatics, digital imaging, electronic commerce, etc. As the final economic and physical barriers to continued increases in silicon-based circuit densities begin to take shape, automated design tools play an ever more important role in determining system performance. Recent studies showed that existing circuit-placement tools are surprisingly far from optimal (70-150% excess wirelength) on simplified circuit benchmarks adapted from real industrial test cases. If this quality gap can be closed, the resulting benefit will be equivalent to advancing several generations in fabrication process technology, the cost of which, when feasible, is normally measured in billions of US dollars. The goal of this research is to develop new, scalable algorithms for VLSI physical design to enable multiple Moore's-Law generations of performance improvement through 3-D design optimization in the presence of complex timing and temperature constraints. The focus in this project will be primarily on circuit placement, as it is the step that most constrains the layout of the interconnect wiring which dominates system performance. The core placement problem is to arrange all circuit elements within a given rectangle such that no two of them overlap and such that a standard estimate of total wirelength is minimized. A broader and deeper analysis of existing algorithms' deviation from optimality and how that deviation changes as design sizes increase will be used to develop a highly efficient and optimized placement engine for the core placement model problem. Scalability of the engine will derive from a multiscale framework, in which objectives and constraints are simultaneously represented and manipulated across a hierarchy of resolution scales. This engine will then be and augmented to handle various complex constraints in both the 2-D and 3-D settings, e.g., signal propagation times, maximum wiring density, maximum temperature, and circuit elements of widely varying sizes.The broader impact of advancing the equivalent of an entire technology generation at almost negligible cost would be considerable. A large jump in raw computing power ultimately translates into new qualitative understanding, as previously intractable problems gradually become solvable. Of potentially even greater impact, moreover, are the possible advances in basic science to be obtained by incorporating detailed physical modeling into a scalable program for optimization over millions of interconnected elements. Ultimately, the vast size and complexity of nanoscale design problems can realistically be approached only by scalable algorithms yet to be developed. The successful formulation of a truly scalable methodology for physically realistic VLSI designs can be expected to have lasting and far-reaching impact on future design paradigms.