NSF Workshop on Challenges and Opportunities in Gig-Scale Integration for System-On-A-Chip

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This workshop, sponsored by the National Science Foundation and the National Science Council of Taiwan, is an assessment of the challenges and critical research needs of design and verification in giga-scale (nanometer) technologies. Rapid scaling of technologies enables a very high degree of chip integration. It will soon be feasible to integrate a complex electronic system on onto a chip, including microprocessors, embeddedmemories, programmable logics, and various application specific circuit components. However, there is no proven design methodology and tools to support such giga-scale design and integration. Research questions being addressed are: How to provide sufficient design abstraction which takes into consideration the electrical details in nanometer design?; How to represent and characterize reusable blocks which can be used across the boundaries of technology generations, foundries and design environments?; How to model the interaction of heterogeneous functional blocks for overall simulation and optimization?; How to certify "known good design" under functional specification and performance constraints? The workshop report contains a statement of the workshop findings with regard to promising opportunities for innovation, and recommendations regarding the style and kind of research to be conducted. It identifies and suggestions to the community as to how to implement the recommendations.