NSF Workshop on Challenges and Opportunities in Gig-Scale Integration for System-On-A-Chip

这个研讨会，由国家科学基金会和台湾国家科学理事会赞助，是一个评估的挑战和关键的研究需求的设计和验证千兆规模（纳米）技术。技术的快速扩展实现了非常高的芯片集成度。将一个复杂的电子系统集成到一块芯片上，包括微处理器、嵌入式存储器、可编程逻辑和各种专用电路元件，很快就可以实现。然而，目前还没有经过验证的设计方法和工具来支持这种千兆级的设计和集成。 研究的问题是：如何提供充分的设计抽象，考虑到纳米设计中的电气细节？ 如何表示和表征可跨越技术世代、铸造厂和设计环境的边界使用的可重复使用块？ 如何对异构功能块的交互进行建模以进行整体仿真和优化？ 如何在功能规格和性能约束下证明“已知良好设计”？ 研讨会报告载有研讨会关于有希望的创新机会的结论说明，以及关于拟进行的研究的风格和种类的建议。它确定并建议社区如何实施这些建议。

This workshop, sponsored by the National Science Foundation and the National Science Council of Taiwan, is an assessment of the challenges and critical research needs of design and verification in giga-scale (nanometer) technologies. Rapid scaling of technologies enables a very high degree of chip integration. It will soon be feasible to integrate a complex electronic system on onto a chip, including microprocessors, embeddedmemories, programmable logics, and various application specific circuit components. However, there is no proven design methodology and tools to support such giga-scale design and integration. Research questions being addressed are: How to provide sufficient design abstraction which takes into consideration the electrical details in nanometer design?; How to represent and characterize reusable blocks which can be used across the boundaries of technology generations, foundries and design environments?; How to model the interaction of heterogeneous functional blocks for overall simulation and optimization?; How to certify "known good design" under functional specification and performance constraints? The workshop report contains a statement of the workshop findings with regard to promising opportunities for innovation, and recommendations regarding the style and kind of research to be conducted. It identifies and suggestions to the community as to how to implement the recommendations.