COLLABORATIVE RESEARCH: Modeling, Simulation, Circuit Design, Logic Synthesis, Testing and Defect Tolerance of Resonant Tunneling Device Based Nanotechnology

合作研究：基于纳米技术的谐振隧道器件的建模、仿真、电路设计、逻辑综合、测试和缺陷容限

• 批准号: 0429745
• 负责人: Niraj Jha
• 金额: $ 12万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0429745&HistoricalAwards=false
• 关键词: COLLABORATIVE; RESEARCH; Modeling; Simulation; Circuit

Proposal No: 429745 Prinipal Investigator: Niraj Jha (Princeton U) and Pinaki Mazumder (U Michigan)Title: COLLABORATIVE RESEARCH: Modeling, Simulation, Circuit Design, Logic Synthesis, Testing and Defect Tolerance of Resonant Tunneling Device based NanotechnologyAbstract:Nanotechnologies, such as resonant-tunneling devices (RTDs), quantum cellular automata, single electron transistors, atom relays, refined molecular relays, carbon nanotube transistors, etc., have seen significant advances in the last few years. They offer orders of magnitude improvements in chip density, performance and power consumption, making many as-yet undreamed-of applications feasible. However, comprehensive circuit analysis/synthesis methodologies and tools have not yet been developed for any nanotechnology. Such tools are urgently needed in order to realize their potential. In this proposal, the investigators will target RTD-based nanotechnology, which has already shown industrial promise. Specifically, we will develop an electronic circuit design optimization environment, and techniques for circuit design, logic synthesis, testing and fault tolerance for this nanotechnology.

提案编号：429745主要研究者：Niraj Jha（普林斯顿大学）和Pinaki Mazumder（密歇根大学）标题：合作研究：建模，仿真，电路设计，逻辑合成，测试和基于纳米技术的共振隧穿器件的缺陷容限摘要：纳米技术，如共振隧穿器件（RTD），量子细胞自动机，单电子晶体管，原子继电器，精制分子继电器，碳纳米管晶体管等，在过去的几年里取得了显著的进步。它们在芯片密度、性能和功耗方面提供了数量级的改进，使许多尚未实现的应用成为可能。然而，全面的电路分析/合成方法和工具尚未开发的任何纳米技术。迫切需要这些工具，以发挥其潜力。在这项提案中，调查人员将目标放在基于RTD的纳米技术上，该技术已经显示出工业前景。具体来说，我们将开发一个电子电路设计优化环境，以及用于这种纳米技术的电路设计，逻辑合成，测试和容错技术。