SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space

SHF：小型：FinFET SRAM 设计空间的寄生感知探索

• 批准号: 1318603
• 负责人: Niraj Jha
• 金额: $ 45万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1318603&HistoricalAwards=false
• 关键词: SHF; Small; Parasitics; aware; Exploration

Planar complementary metal-oxide-semiconductor (CMOS) technology scaling is coming to an end with the adoption of FinFETs (a type of field-effect transistor or FET) at the 22nm technology node and beyond. As a result of having multiple gates wrapped around the fin body, FinFETs exhibit better control of the channel potential with scaling, thereby alleviating the explosive leakage current problem faced by planar short-channel devices. Since static random access memory (SRAM) bit-cells are often the densest features patterned on an integrated circuit, researchers have begun investigating the design and manufacturability of FinFET SRAMs. Most of these investigations focus on enhancing/contrasting SRAM direct current (DC) metric targets. However, such metrics are not an accurate guide to FinFET bit-cell designers, as parasitic capacitances for two topologically equivalent bit-cells can be very different (due to differing fin pitches, etc.), resulting in widely varying transient characteristics. Thus, in order to predict array-scale metrics through simulation, capturing transient behavior accurately is absolutely essential. To accomplish the latter, SRAM parasitic capacitances need to be extracted accurately from the layout. Using an accurate parasitic capacitance extraction method that the principal investigator's (PI's) group has developed, the project plans to explore the FinFET SRAM design space from both DC metrics and transient behavior points of view, under process-voltage-temperature variations. Since SRAMs account for more than 50% of the area of modern microprocessors, it is very important to base them on the best SRAM bit-cell design. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are to be developed will be disseminated through the web. Technology transfer will be done through various companies the PI interacts with. The material will be included in a course on Design with Nanotechnologies that the PI teaches. Princeton has a tradition of undergraduate independent research. Many seniors are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program. The PI has supervised 10 female Ph.D. students so far. Further outreach activities are also planned for high-school students. The PI has supervised the research of four high-school students in the last two years, including a female student.

平面互补金属氧化物半导体（CMOS）技术规模化随着FinFET（场效应晶体管或FET的一种）在22纳米技术节点及更高技术节点的采用而即将结束。由于具有围绕鳍主体缠绕的多个栅极，FinFET表现出对沟道电势随缩放的更好控制，从而减轻平面短沟道器件所面临的爆炸性漏电流问题。由于静态随机存取存储器（SRAM）位单元通常是集成电路上图案化的致密特征，研究人员已经开始研究FinFET SRAM的设计和可制造性。大多数这些调查集中在增强/对比SRAM直流（DC）度量目标。然而，这样的度量不是FinFET位单元设计者的准确指南，因为两个拓扑上等效的位单元的寄生电容可能非常不同（由于不同的鳍节距等），导致瞬态特性变化很大。因此，为了通过仿真预测阵列规模的指标，准确地捕捉瞬态行为是绝对必要的。为了实现后者，需要从布局中准确地提取SRAM寄生电容。该项目计划使用首席研究员（PI）团队开发的精确寄生电容提取方法，从直流指标和瞬态行为的角度探索FinFET SRAM设计空间，并在工艺电压温度变化下进行研究。由于SRAM占现代微处理器面积的50%以上，因此基于最佳SRAM位单元设计非常重要。因此，这项工作的成功结束，应该是非常有益的半导体工业。拟开发的设计/方法/工具将通过网络传播。技术转让将通过PI与之互动的各种公司进行。该材料将包括在PI教授的纳米技术设计课程中。普林斯顿大学有本科生独立研究的传统。许多老年人都希望做他们的研究项目在这个主题。女性和少数民族学生将通过普林斯顿大学的总统奖学金计划被吸引到这项研究中。PI已经指导了10名女博士。学生至今。还计划为高中学生开展进一步的外联活动。在过去两年中，PI监督了对四名高中生的研究，其中包括一名女生。