SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space

平面互补金属氧化物半导体（CMOS）技术在22nm及以上节点采用了finfet（场效应晶体管或FET的一种），从而结束了技术的缩放。由于在翅片体周围包裹了多个栅极，finfet通过缩放可以更好地控制通道电位，从而减轻了平面短通道器件所面临的爆炸漏电流问题。由于静态随机存取存储器（SRAM）位单元通常是集成电路上密度最大的特征，研究人员已经开始研究FinFET SRAM的设计和可制造性。这些研究大多集中在增强/对比SRAM直流（DC）度量指标上。然而，这些指标并不是FinFET位单元设计者的准确指南，因为两个拓扑等效位单元的寄生电容可能非常不同（由于不同的鳍间距等），导致瞬态特性变化很大。因此，为了通过模拟预测阵列尺度指标，准确捕获瞬态行为是绝对必要的。为了实现后者，需要从布局中准确地提取SRAM寄生电容。该项目计划利用PI小组开发的精确寄生电容提取方法，从直流指标和瞬态行为角度探索工艺电压-温度变化下FinFET SRAM的设计空间。由于SRAM占现代微处理器面积的50%以上，因此基于最佳SRAM位单元设计非常重要。因此，这项工作的成功结束将对半导体工业非常有益。将要开发的设计/方法/工具将通过网络传播。技术转让将通过PI与之互动的不同公司来完成。材料将包括在设计与纳米技术的课程，PI教。普林斯顿大学有本科生独立研究的传统。许多高年级学生都被要求做关于这个主题的研究项目。女性和少数族裔学生将通过普林斯顿大学的总统奖学金项目被吸引到这项研究中来。到目前为止，PI已经指导了10名女博士生。还计划为高中生开展进一步的外联活动。在过去的两年里，PI监督了四名高中生的研究，其中包括一名女学生。

Planar complementary metal-oxide-semiconductor (CMOS) technology scaling is coming to an end with the adoption of FinFETs (a type of field-effect transistor or FET) at the 22nm technology node and beyond. As a result of having multiple gates wrapped around the fin body, FinFETs exhibit better control of the channel potential with scaling, thereby alleviating the explosive leakage current problem faced by planar short-channel devices. Since static random access memory (SRAM) bit-cells are often the densest features patterned on an integrated circuit, researchers have begun investigating the design and manufacturability of FinFET SRAMs. Most of these investigations focus on enhancing/contrasting SRAM direct current (DC) metric targets. However, such metrics are not an accurate guide to FinFET bit-cell designers, as parasitic capacitances for two topologically equivalent bit-cells can be very different (due to differing fin pitches, etc.), resulting in widely varying transient characteristics. Thus, in order to predict array-scale metrics through simulation, capturing transient behavior accurately is absolutely essential. To accomplish the latter, SRAM parasitic capacitances need to be extracted accurately from the layout. Using an accurate parasitic capacitance extraction method that the principal investigator's (PI's) group has developed, the project plans to explore the FinFET SRAM design space from both DC metrics and transient behavior points of view, under process-voltage-temperature variations. Since SRAMs account for more than 50% of the area of modern microprocessors, it is very important to base them on the best SRAM bit-cell design. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are to be developed will be disseminated through the web. Technology transfer will be done through various companies the PI interacts with. The material will be included in a course on Design with Nanotechnologies that the PI teaches. Princeton has a tradition of undergraduate independent research. Many seniors are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program. The PI has supervised 10 female Ph.D. students so far. Further outreach activities are also planned for high-school students. The PI has supervised the research of four high-school students in the last two years, including a female student.