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SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space

SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space
SHF:小型:FinFET SRAM 设计空间的寄生感知探索
批准号:
1318603
负责人:
Niraj Jha
金额:
$45.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-09-01 至 2017-08-31

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中文摘要
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英文摘要
Planar complementary metal-oxide-semiconductor (CMOS) technology scaling is coming to an end with the adoption of FinFETs (a type of field-effect transistor or FET) at the 22nm technology node and beyond. As a result of having multiple gates wrapped around the fin body, FinFETs exhibit better control of the channel potential with scaling, thereby alleviating the explosive leakage current problem faced by planar short-channel devices. Since static random access memory (SRAM) bit-cells are often the densest features patterned on an integrated circuit, researchers have begun investigating the design and manufacturability of FinFET SRAMs. Most of these investigations focus on enhancing/contrasting SRAM direct current (DC) metric targets. However, such metrics are not an accurate guide to FinFET bit-cell designers, as parasitic capacitances for two topologically equivalent bit-cells can be very different (due to differing fin pitches, etc.), resulting in widely varying transient characteristics. Thus, in order to predict array-scale metrics through simulation, capturing transient behavior accurately is absolutely essential. To accomplish the latter, SRAM parasitic capacitances need to be extracted accurately from the layout. Using an accurate parasitic capacitance extraction method that the principal investigator's (PI's) group has developed, the project plans to explore the FinFET SRAM design space from both DC metrics and transient behavior points of view, under process-voltage-temperature variations. Since SRAMs account for more than 50% of the area of modern microprocessors, it is very important to base them on the best SRAM bit-cell design. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are to be developed will be disseminated through the web. Technology transfer will be done through various companies the PI interacts with. The material will be included in a course on Design with Nanotechnologies that the PI teaches. Princeton has a tradition of undergraduate independent research. Many seniors are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program. The PI has supervised 10 female Ph.D. students so far. Further outreach activities are also planned for high-school students. The PI has supervised the research of four high-school students in the last two years, including a female student.
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