Application-specific Instruction Set Processor Synthesis for Low Energy and High Performance using Extensible Processor Platforms

所提出的研究的目的是调查和开发一个全面的框架，自动合成的定制处理器。所提出的框架的范围包括从需要执行的一个或多个嵌入式软件程序开始生成定制处理器架构的所有必要步骤。我们要解决的问题如下。我们将为大型层次化应用程序开发有效的自动生成硬件扩展的技术，这些扩展包括自定义指令和协处理器到基本处理器平台。现实的应用软件的复杂性，再加上多粒度的性质的硬件扩展，需要开发新的技术，从一个层次的程序表示，并确定自定义的指令和协处理器，最大限度地提高性能或最小化的能源消耗在给定的设计约束。个别候选定制指令和协处理器的数目对于甚至中等大小的程序来说可相当大，且因此其组合的数目甚至更大。 我们将开发技术来有效地探索统一的自定义指令和协处理器设计空间，并选择自定义指令和协处理器的最佳组合（从单个候选者中），以最大限度地提高性能或能源效率。 高水平的硬件重用对于获得定制处理器的高效实现至关重要。 针对给定应用导出的各种定制指令可展现出可被利用来在给定面积约束下减少面积开销或改善性能/能量影响的共性。除了传统的细粒度资源共享技术，我们将开发新的粗粒度共享技术，以获得高质量的设计。 如果在尝试导出硬件扩展之前适当地应用于目标应用程序，则软件转换可以促进更高质量的定制指令或协处理器的生成，从而导致更高的性能和能量增益。 我们将开发一种方法来自动地对应用程序应用一个合适的启用转换序列。 效率和灵活性是驱动嵌入式系统设计的两个主要要求。不幸的是，这两个要求通常彼此冲突-性能和能量效率通常通过硬连线功能和以特定于应用的方式优化系统来获得，这限制了灵活性，而灵活性通过可配置性和/或可编程性来获得，这带来了相关的开销。在从高性能系统到电池驱动系统的各种应用中，协商这种权衡至关重要。 专用指令集处理器（ASIP）通过使用定制硬件仅实现感兴趣的应用程序中的关键操作，在效率和灵活性之间提供了良好的折衷。 ASIP设计的传统方法是基于为每个应用程序从头开始设计和实现新的指令集和处理器架构。不幸的是，此类方法的设计周转时间可能很长，并且与定制硬件实现的设计周期相当。可定制和可扩展处理器技术的最新发展，例如Tensilica的Xtensa和ARC的ARCTangent处理器内核，为嵌入式系统设计人员提供了一种机制，通过使用可重定向的软件开发工具流程和可配置的软知识产权（IP）来设计具有快速周转时间的ASIP。然而，定制处理器并使用定制硬件（指令单元、协处理器、外围设备）对其进行扩展的任务在很大程度上仍然是手动的，并留给设计师的专业知识。为了实现ASIP提供的能源效率和灵活性的潜力，有必要开发高级方法，自动识别应用热点并将其映射到扩展底层可配置平台的自定义硬件。 不存在用于可扩展处理器平台的解决上述问题中的任何一个的算法或工具。 我们已经朝着这个方向迈出了第一步，开发了算法和工具来自动识别可扩展处理器的自定义指令。该工具的平均性能提高了3.4倍（高达5.4倍），平均能量延迟产品提高了12.6倍（高达24.2倍）。

The objective of the proposed research is to investigate and develop a comprehensive framework for the automatic synthesis of custom processors. The scope of the proposed framework includes all the necessary steps to generate the custom processor's architecture, starting from one or more embedded software programs that it is required to execute. The problems that we will tackle are as follows. We will develop techniques for efficient automatic generation of hardware extensions -- custom instructions and co-processors -- to a base processor platform, for large hierarchical application programs. The complexity of realistic application software, together with the multi-granular nature of the hardware extensions, necessitate the development of new techniques that start from a hierarchical program representation and identify custom instructions and co-processors that maximize performance or minimize energy consumption under given design constraints. The number of individual candidate custom instructions and co-processors can be quite large for even moderately sized programs, and hence the number of combinations thereof is even larger. We will develop techniques to efficiently explore the unified custom instruction and co-processor design space, and select an optimal combination of custom instructions and co-processors (from individual candidates) that maximizes performance or energy efficiency. High levels of hardware re-use are critical for deriving efficient implementations of custom processors. Various custom instructions derived for a given application may exhibit commonality that can be exploited to either reduce the area overhead or improve performance/energy impact under a given area constraint. In addition to conventional fine-grained resource sharing techniques, we will develop new coarse-grained sharing techniques to obtain high quality designs. Software transformations, if appropriately applied to the target application program before attempting to derive hardware extensions, can facilitate the generation of higher quality custom instructions or co-processors, leading to much higher performance and energy gains. We will develop a method to automatically apply a suitable sequence of enabling transformations to the application. Efficiency and flexibility are two major requirements driving embedded system design. Unfortunately, these two requirements are typically at conflict with each other - performance and energy efficiency are often obtained by hardwiring functionality and optimizing the system in an application-specific manner, which limits flexibility, while flexibility is obtained through configurability and/or programmability, which carry associated overheads. Negotiating this tradeoff is critical in a wide variety of applications, ranging from high-performance systems to battery-driven systems. Application-specific instruction set processors (ASIPs) offer a good tradeoff between efficiency and flexibility by realizing only the critical operations in the application(s) of interest using custom hardware. Conventional approaches to ASIP design are based on designing and implementing a new instruction set and processor architecture from scratch for each application. Unfortunately, the design turnaround time for such approaches may be large and is comparable to design cycles for custom hardware implementations. The recent evolution of customizable and extensible processor technology, such as Tensilica's Xtensa and ARC's ARCTangent processor cores, has provided embedded system designers with a mechanism to design ASIPs with rapid turnaround times through the use of re-targetable software development tool flows, and configurable soft intellectual property (IP). However, the task of customizing the processor and extending it with custom hardware (instruction units, co-processors, peripherals) are still largely manual and left to the designer's expertise. In order to realize the potential for energy efficiency as well as flexibility that ASIPs offer, it is necessary to develop high-level methodologies that automatically identify application hot-spots and map them to custom hardware that extends the underlying configurable platform. No algorithms or tools exist for extensible processor platforms that address any of the above problems. We have taken the first step in this direction by developing algorithms and a tool to automatically identify custom instructions for extensible processors. This tool results in an average performance improvement of 3.4X (up to 5.4X) and an average energy-delay product improvement of 12.6X (up to 24.2X).