SHF: Small: Exploration of the Transistor-level Monolithic 3D SRAM Design Space

静态随机存取存储器（sram）是现代微处理器的重要组成部分，占其面积的一半以上。它们是内存层次结构的一部分，使应用程序能够在这些处理器上加速。由于传统的二维集成电路（IC）正在失去动力，未来十年的另一种选择将是垂直发展，即在同一IC封装中具有多层逻辑和存储器。有两种方法可以实现3D：使用硅通孔（tsv）或单片3D集成。由于单片3D集成比基于TSV的3D集成具有许多优势，因此本研究的目标是前者。特别是，它的目的是探索晶体管级单片（TLM） 3D sram在现代半导体技术finfet中实现的设计空间。因此，这项工作的成功结束将对半导体工业非常有益。所开发的设计/方法/工具将在网上提供。它们还将通过PI与之互动的各种公司传播到该行业。这些材料将包含在PI教授的课程中。许多高年级学生的论文都是关于这个主题的。女性和少数族裔博士生将通过普林斯顿奖学金被吸引到这项研究中来。还计划为高中生开展进一步的外联活动。结果将通过研究文章和讨论会传播。在TLM设计风格中，n型和p型晶体管可以放置在不同的层上，从而显着减少SRAM位元的占地面积。这也使两层的单独优化成为可能，这具有提高SRAM单元稳定性的额外优势。稳定性是sram的一个非常重要的指标，因为它们将半导体技术推向其极限，以便在微处理器中容纳尽可能多的内存。然而，在TLM FinFET SRAM位元设计领域的探索几乎没有任何工作。提出的工作通过精确的电容提取和器件仿真来填补这一空白，在IC上的工艺电压-温度变化。

Static random-access memories (SRAMs) constitute an important part of modern microprocessors, occupying more than half of its area. They are part of the memory hierarchy that enables applications to be sped up on these processors. Since traditional 2D scaling of integrated circuits (ICs) is running out of steam, an alternative in the coming decade would be to go vertical, i.e., have several layers of logic and memory in the same IC package. There are two ways to go 3D: using through-silicon vias (TSVs) or monolithic 3D integration. Since monolithic 3D integration enjoys many advantages over TSV based 3D integration, this work is aimed at the former. In particular, its aim is to explore the design space of transistor-level monolithic (TLM) 3D SRAMs implemented in the modern semiconductor technology of FinFETs. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are developed will be made available on the web. They will also be disseminated to the industry through various companies the PI interacts with. The material will be included in a course that the PI teaches. Many seniors are expected to do their thesis on this topic. Female and minority PhD students will be attracted to this research through Princeton Fellowships available for this purpose. Further outreach activities are also planned for high-school students. Results will be disseminated through research articles and seminars.In the TLM design style, the n-type and p-type transistors can be placed on different layers, thus reducing the footprint area of an SRAM bitcell significantly. This also enables separate optimizations of the two layers, which has the added advantage of improving stability of SRAM cells. Stability is a very important metric for SRAMs since they push the semiconductor technology to its limits in order to accommodate as much memory into the microprocessor as possible. However, there is hardly any work on the TLM FinFET SRAM bitcell design space exploration. The proposed work fills this gap through accurate capacitance extraction and device simulation, under process-voltage-temperature variations on the IC.