SHF: Small: Exploration of the Transistor-level Monolithic 3D SRAM Design Space

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Static random-access memories (SRAMs) constitute an important part of modern microprocessors, occupying more than half of its area. They are part of the memory hierarchy that enables applications to be sped up on these processors. Since traditional 2D scaling of integrated circuits (ICs) is running out of steam, an alternative in the coming decade would be to go vertical, i.e., have several layers of logic and memory in the same IC package. There are two ways to go 3D: using through-silicon vias (TSVs) or monolithic 3D integration. Since monolithic 3D integration enjoys many advantages over TSV based 3D integration, this work is aimed at the former. In particular, its aim is to explore the design space of transistor-level monolithic (TLM) 3D SRAMs implemented in the modern semiconductor technology of FinFETs. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are developed will be made available on the web. They will also be disseminated to the industry through various companies the PI interacts with. The material will be included in a course that the PI teaches. Many seniors are expected to do their thesis on this topic. Female and minority PhD students will be attracted to this research through Princeton Fellowships available for this purpose. Further outreach activities are also planned for high-school students. Results will be disseminated through research articles and seminars.In the TLM design style, the n-type and p-type transistors can be placed on different layers, thus reducing the footprint area of an SRAM bitcell significantly. This also enables separate optimizations of the two layers, which has the added advantage of improving stability of SRAM cells. Stability is a very important metric for SRAMs since they push the semiconductor technology to its limits in order to accommodate as much memory into the microprocessor as possible. However, there is hardly any work on the TLM FinFET SRAM bitcell design space exploration. The proposed work fills this gap through accurate capacitance extraction and device simulation, under process-voltage-temperature variations on the IC.