SHF: Small:Extremely Energy-Efficient Monolithic 3D System Architectures

SHF：小型：极其节能的单片 3D 系统架构

• 批准号: 1811109
• 负责人: Niraj Jha
• 金额: $ 45万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2018
• 资助国家: 美国
• 起止时间: 2018-07-01 至 2022-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1811109&HistoricalAwards=false
• 关键词: SHF; Small; Extremely; Energy; Efficient

With the slowing down of Moore's Law, traditional 2D scaling is not expected to deliver the area, power, and performance benefits the semiconductor industry has been counting on. Thus, the time has come to go vertical, accommodating processor cores, accelerators, cache, and main memory in the same package. There are two ways of doing this: use through-silicon vias (TSVs) or monolithic 3D integration. TSVs do not have memory-on-logic stacking success stories. Monolithic 3D integration uses monolithic inter-tier vias that have a much smaller diameter than TSVs, and enable many different design styles: transistor-level monolithic, gate-level monolithic, and block-level monolithic. While fabrication and test techniques for monolithic 3D integration are maturing, monolithic 3D system architectures have not been investigated in depth. The work on this project fills this gap. The methodologies and tools developed under this grant will be made available on the web. They will also be made available to the industry. The material will be included in course materials, and under-represented graduate students will be attracted to this research through Princeton Fellowships. Results will be disseminated through research articles and seminars.There are various "walls" confronting computer system architects these days. The Power Wall constrains the portion of the chip that can be powered on. This is also known as the dark silicon problem. The Memory Wall prevents efficient access to off-chip memory. Monolithic 3D integration has the potential to significantly alleviate the problems associated with these walls, especially for abundant-data problems, such as machine learning and inference, which are becoming commonplace. This project seeks to improve the energy efficiency of monolithic 3D system architectures by a factor of 500 relative to traditional system architectures. It will do so by exploiting synergies across the device, logic, memory, accelerator, micro-architecture, chip multiprocessor, and monolithic 3D IC levels of the design hierarchy, providing a common computation platform from high-performance mobile devices to data centers.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着摩尔定律的放缓，传统的2D扩展预计不会带来半导体行业一直指望的面积、功率和性能方面的好处。因此，将处理器核心、加速器、高速缓存和主存放在同一个封装中的垂直方向已经到来。有两种方法可以做到这一点：使用直通硅通孔(TSV)或单片3D集成。TSV没有逻辑上存储堆叠的成功案例。单片3D集成使用直径比TSV小得多的单片层间通孔，并支持多种不同的设计风格：晶体管级单片、门级单片和块级单片。虽然单片3D集成的制造和测试技术日趋成熟，但单片3D系统架构还没有得到深入的研究。这个项目的工作填补了这一空白。在这笔赠款下开发的方法和工具将在网上提供。它们也将向该行业提供。这些材料将包括在课程材料中，代表不足的研究生将通过普林斯顿奖学金被吸引到这项研究中。结果将通过研究文章和研讨会传播。如今，计算机系统架构师面临着各种各样的“墙”。电源墙限制了芯片中可以通电的部分。这也被称为暗硅问题。存储墙阻止了对片外存储器的有效访问。整体3D集成有可能显著缓解与这些墙相关的问题，特别是对于机器学习和推理等海量数据问题，这些问题正变得司空见惯。该项目旨在将单片3D系统体系结构的能效提高到传统系统体系结构的500倍。它将通过利用设计层次的设备、逻辑、内存、加速器、微体系结构、芯片多处理器和单片3D IC级别的协同效应来实现这一点，提供从高性能移动设备到数据中心的通用计算平台。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。