SHF:Small: Fine-grain Dynamically Reconfigurable FPGA Architecture Aimed at Reducing the ASIC-FPGA Gaps

SHF:Small：旨在缩小 ASIC-FPGA 差距的细粒度动态可重构 FPGA 架构

• 批准号: 1216457
• 负责人: Niraj Jha
• 金额: $ 35万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1216457&HistoricalAwards=false
• 关键词: SHF; Small; Fine; grain; Dynamically

Field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are two very important processing elements for computation. FPGAs are very attractive because of their lower design cost and shorter time-to-market compared to ASICs. Still, the marketshare of FPGAs remains less than a fifth of that of ASICs because ASICs enjoy an advantage over FPGAs in terms of circuit area, power consumption, and delay. The objective of the proposed work is to significantly reduce these area/power/delay gaps through a new dynamically reconfigurable FPGA design and thus enable FPGAs to become much more competitive with ASICs. Continued scaling of bulk CMOS technology faces significant hurdles. To alleviate these problems, Intel and TSMC have already announced a switch to multi-gate field-effect transistors, e.g., Trigate and FinFETs, at the upcoming semiconductor technology nodes. Another important trend is towards 3D integrated circuits (ICs), in which multiple die layers are stacked on top of each other. 3D ICs promise a revolution in so called ``More than Moore" computing. The proposed work aims to take advantage of the multi-gate and 3D IC technologies to further reduce the gaps mentioned above.The proposed FPGA architecture significantly deviates from the conventional island-style FPGA architecture by enabling the logic element to either perform computation or local communication or both. It is aided by the key concept of temporal logic folding that allows a circuit to be drastically folded, aided by on-chip reconfiguration memory, before being mapped to the FPGA. It attacks the main reason for the area/power/delay gaps -- the vast amount of chip resources allocated to reconfigurable interconnects in FPGAs. Logic folding makes the communication local, thus making it possible to reduce the amount of resources devoted to interconnects very significantly. The work entails design space exploration of the different components of the architecture, investigation of novel multi-gate computation/communication structures, and algorithms and design automation tools to map arbitrary circuits to the FPGA architecture. It is expected to yield a well-characterized and highly versatile family of 3D multi-gate transistor based FPGAs that are competitive with ASICs. Work on various design methodologies and tools developed in this research will be disseminated through conference and journal articles. Technology transfer will be done through companies interested in using such FPGAs as accelerators. The material will be included in a senior-level course on Design with Nanotechnologies and a graduate-level course on Low Power IC and System Design introduced by the PI. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program.

现场可编程门阵列（FPGA）和专用集成电路（ASIC）是两种非常重要的计算处理元件。FPGA非常有吸引力，因为与ASIC相比，其设计成本更低，上市时间更短。 尽管如此，FPGA的市场份额仍然不到ASIC的五分之一，因为ASIC在电路面积、功耗和延迟方面比FPGA具有优势。 所提出的工作的目标是显着减少这些面积/功耗/延迟差距，通过一个新的动态可重构的FPGA设计，从而使FPGA变得更具竞争力的ASIC。体CMOS技术的持续扩展面临重大障碍。为了缓解这些问题，英特尔和台积电已经宣布转向多栅极场效应晶体管，例如，即将到来的半导体技术节点上的三角栅和FinFET。 另一个重要的趋势是朝向3D集成电路（IC），其中多个管芯层堆叠在彼此的顶部上。 三维集成电路有望在所谓的“超过摩尔”计算领域掀起一场革命。 本文的工作旨在利用多门和3D集成电路技术进一步缩小上述差距，使逻辑元件能够执行计算或本地通信或两者兼而有之，从而大大偏离了传统的岛式FPGA结构。 它是由时序逻辑折叠的关键概念，允许一个电路被大幅折叠，片上重新配置存储器的帮助下，被映射到FPGA的帮助。它攻击了面积/功耗/延迟差距的主要原因-分配给FPGA中可重新配置互连的大量芯片资源。 逻辑折叠使得通信本地化，从而使得可以非常显著地减少用于互连的资源量。这项工作需要设计空间探索的架构，新的多门计算/通信结构的调查，算法和设计自动化工具，以映射任意电路的FPGA架构的不同组成部分。它有望产生一个具有良好特性和高度通用性的基于3D多栅极晶体管的FPGA系列，与ASIC竞争。 在这项研究中开发的各种设计方法和工具的工作将通过会议和期刊文章传播。 技术转让将通过有兴趣使用此类FPGA作为加速器的公司进行。这些材料将被纳入PI介绍的纳米技术设计高级课程和低功耗IC和系统设计研究生课程。女性和少数民族学生将通过普林斯顿大学的总统奖学金计划被吸引到这项研究中。