SHF:Small: Fine-grain Dynamically Reconfigurable FPGA Architecture Aimed at Reducing the ASIC-FPGA Gaps

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Field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are two very important processing elements for computation. FPGAs are very attractive because of their lower design cost and shorter time-to-market compared to ASICs. Still, the marketshare of FPGAs remains less than a fifth of that of ASICs because ASICs enjoy an advantage over FPGAs in terms of circuit area, power consumption, and delay. The objective of the proposed work is to significantly reduce these area/power/delay gaps through a new dynamically reconfigurable FPGA design and thus enable FPGAs to become much more competitive with ASICs. Continued scaling of bulk CMOS technology faces significant hurdles. To alleviate these problems, Intel and TSMC have already announced a switch to multi-gate field-effect transistors, e.g., Trigate and FinFETs, at the upcoming semiconductor technology nodes. Another important trend is towards 3D integrated circuits (ICs), in which multiple die layers are stacked on top of each other. 3D ICs promise a revolution in so called ``More than Moore" computing. The proposed work aims to take advantage of the multi-gate and 3D IC technologies to further reduce the gaps mentioned above.The proposed FPGA architecture significantly deviates from the conventional island-style FPGA architecture by enabling the logic element to either perform computation or local communication or both. It is aided by the key concept of temporal logic folding that allows a circuit to be drastically folded, aided by on-chip reconfiguration memory, before being mapped to the FPGA. It attacks the main reason for the area/power/delay gaps -- the vast amount of chip resources allocated to reconfigurable interconnects in FPGAs. Logic folding makes the communication local, thus making it possible to reduce the amount of resources devoted to interconnects very significantly. The work entails design space exploration of the different components of the architecture, investigation of novel multi-gate computation/communication structures, and algorithms and design automation tools to map arbitrary circuits to the FPGA architecture. It is expected to yield a well-characterized and highly versatile family of 3D multi-gate transistor based FPGAs that are competitive with ASICs. Work on various design methodologies and tools developed in this research will be disseminated through conference and journal articles. Technology transfer will be done through companies interested in using such FPGAs as accelerators. The material will be included in a senior-level course on Design with Nanotechnologies and a graduate-level course on Low Power IC and System Design introduced by the PI. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program.