Hierarchical Test Generation and Design For Testability of Core-Based Systems

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This research is on hierarchical and symbolic test generation and design for testability techniques for core- based systems. The system can be a combination of soft, firm and hard cores. In the case of untestable soft cores, hierarchical testability techniques are being applied to make them testable. Also techniques of adding hardware so the cores are functionally transparent and can propagate test data without information loss are being developed. The approach is to integrate testable and transparent cores to ensure justification of precomputed test sequences. This test generation approach is independent of the bit-width of the cores. The case of firm and hard cores which have testability features built into them by core providers is also being explored. Approaches here include: using information supplied by the core vendor; use of in-built testability features; and providing transparency through glue logic outside the core.