SHF: SMALL: Collaborative Research: Reconfigurable and Programmable Processor Architectures for Brain-Computer Interfacing

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One of the primary motivations of brain-computer interfaces (BCIs) is to restore behavioral functions for patients who are unable to move or communicate through normal neural pathways because of strokes or chronic diseases. Restoring a full range of movements for paralyzed patients requires recordings from a relatively large population of brain neurons. Wireless transmission of large amounts of neural data for off-line processing on a computer imposes heat-related tissue damage and hinders real-time control of the prosthetics. In this SHF collaborative research, a foundation is laid for finding an optimal balance between real-time neural-signal processing using a brain-implantable electronic device and wireless data transmission for offline processing on a machine or computer so that the total power/energy consumption of the brain-implanted integrated circuit is minimized. This research focuses on a transformative BCI-specific processor architecture utilizing custom digital circuits to drastically relax power-hungry wireless data transmission while controlling prosthetics in real-time. The impact of research findings on education and society include: broadening the participation of underrepresented high school students using the new "Brain Chips" outreach program; enhancing educational learning via the "lab-at-home" approach; engaging the local community and broader society, especially those with disabilities, via workshops at the Disability Center San Diego; and contributing to rehabilitation and improving the quality of life of millions of patients suffering from neurodegenerative diseases or paralysis.This research creates a hybrid processor that is both software-programmable to efficiently execute neural-signal processing algorithms and hardware-reconfigurable to adopt a configurable instruction set architecture (ISA). The software-programmability supports the continuing evolution of approaches and algorithmic improvements while utilizing lower silicon area. Rather than optimized algorithms mapped onto a fixed-processor architecture, the processor optimally matches the specific requirements of the BCI algorithms at runtime by adopting a configurable ISA instead of a fixed and predetermined set of instructions and hence attains greater energy efficiency. The processor also utilizes various dedicated hardware architectures, including artificial and spiking neural networks, for area and energy-efficient processing of neural signals, transmitting only the translated commands directly to prosthetic devices and thus, minimizing the wireless communication overhead.To find and assess candidate neural-signal processing algorithms for real-time operation on the brain-implantable processor, this multidisciplinary research boosts the search in the large design space of neural-signal processing via a software-based performance and accuracy analysis tool that will reliably measure their important characteristics. By quantitatively comparing the potential neural-signal processing algorithms using meaningful efficiency and accuracy metrics, the BCI-specific processor and dedicated hardware architectures will be optimized for energy-efficient operation. The hybrid processor architecture and the design specifications are optimized by testing the BCI system at the Washington National Primate Research Center at the University of Washington in macaque monkeys.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.