CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System on a Chip
职业:职业发展计划:混合信号片上系统的行为建模、仿真和优化
基本信息
- 批准号:0448534
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:美国
- 项目类别:Continuing Grant
- 财政年份:2005
- 资助国家:美国
- 起止时间:2005-06-01 至 2012-05-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
AbstractNSF Proposal#: 0448534Dr. Xiang-Dong (Sheldon Tan) TanUniversity of California at RiversideThis research seeks to develop an integrated research and education program on behavioral modeling, simulation, and optimization techniques to address and overcome the mixed-signal (MS) system-on-a-chip (SoC) design challenges and enable a leap to a new generation of mixed-signal VLSI systems. The focus is to develop efficient techniques for modeling, simulation and optimization of MS SoCs designs, which consist of both analog and digital blocks and operates in mixed frequency ranges (base-band frequency or radio frequency (RF)). The project specifically targets at (a) development of efficient parametric behavioral modeling and hierarchical piecewise linear (PWL) nonlinear modeling techniques based on a graph-based approach for linear and nonlinear analog circuits; (b) investigation of efficient algorithms for optimizing analog circuits and on-chip power-delivery systems for MS-SoC circuits based on modeling techniques. The new modeling techniques will explore a determinant-design diagram (DDD) based symbolic analysis method to construct behavioral models that consider device parameter ranges and design variations to cope with increasing manufacture uncertainty. For modeling nonlinear analog circuits, DDD-based hierarchical piece wise linear (PWL) modeling techniques will be investigated, which promises high fidelity behavioral modeling of very large nonlinear circuits at various abstract levels. As more physical effects become prominent, design practice, especially for the analog circuits, has become an optimization-like process because performance, reliability and manufacturability specifications have to be satisfied or optimized simultaneously. Such optimization-like design paradigms require new different design strategies and methodologies from that of digital circuits and will be explored in this research.The education component of the program consists of development of new curriculum in behavioral modeling, simulation and optimization of MS SoCs, and exploration of innovative learning approaches via web-enabled instructional tools and project-oriented learning for the education of future engineers with the knowledge of behavioral modeling, design and verification for mixed-signal SoCs. Engineers very versed in MS VLSI design and MS CAD development will be trained under this research project.
摘要NSF提案编号:0448534 Dr. Tan Xiang-Dong(谢尔顿Tan)加州大学河滨分校本研究旨在开发一个关于行为建模、仿真和优化技术的综合研究和教育项目,以解决和克服混合信号(MS)片上系统(SoC)设计挑战,并实现向新一代混合信号VLSI系统的飞跃。重点是开发用于MS SoC设计的建模,仿真和优化的有效技术,这些设计由模拟和数字模块组成,并在混合频率范围(基带频率或射频(RF))中工作。 该项目的具体目标是(a)基于线性和非线性模拟电路的基于图的方法开发高效的参数行为建模和分层分段线性(PWL)非线性建模技术;(B)基于建模技术研究用于优化模拟电路和MS-SoC电路的片上功率传输系统的高效算法。新的建模技术将探索一个决定性的设计图(DDD)为基础的符号分析方法,以构建行为模型,考虑器件参数范围和设计变化,以科普日益增加的制造不确定性。为了对非线性模拟电路进行建模,将研究基于DDD的分层分段线性(PWL)建模技术,该技术承诺在各种抽象级别上对非常大的非线性电路进行高保真度的行为建模。随着越来越多的物理效应变得突出,设计实践,特别是对于模拟电路,已经成为一个类似优化的过程,因为性能,可靠性和可制造性规格必须同时满足或优化。这种类似优化的设计范式需要新的不同于数字电路的设计策略和方法,并将在本研究中进行探索。该计划的教育部分包括开发MS SoC行为建模,仿真和优化的新课程,通过网络教学工具和项目探索创新的学习方法-面向未来工程师的教育,具有混合信号SoC的行为建模,设计和验证知识。 在此研究项目下,将培训精通MS VLSI设计和MS CAD开发的工程师。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Sheldon Tan其他文献
Sheldon Tan的其他文献
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{{ truncateString('Sheldon Tan', 18)}}的其他基金
SHF:Small: Learning-based Fast Analysis and Fixing for Electromigration Damage
SHF:Small:基于学习的电迁移损伤快速分析和修复
- 批准号:
2305437 - 财政年份:2023
- 资助金额:
-- - 项目类别:
Standard Grant
SHF:Small: Data-Driven Thermal Monitoring and Run-Time Management for Manycore Processor and Chiplet Designs
SHF:Small:适用于多核处理器和小芯片设计的数据驱动热监控和运行时管理
- 批准号:
2113928 - 财政年份:2021
- 资助金额:
-- - 项目类别:
Standard Grant
SHF:Small: Machine Learning Approach for Fast Electromigration Analysis and Full-Chip Assessment
SHF:Small:用于快速电迁移分析和全芯片评估的机器学习方法
- 批准号:
2007135 - 财政年份:2020
- 资助金额:
-- - 项目类别:
Standard Grant
IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design
IRES Track I:通过可靠性意识 IC 设计合作研究促进全球科学家和工程师的发展
- 批准号:
1854276 - 财政年份:2019
- 资助金额:
-- - 项目类别:
Standard Grant
SHF:Small: EM-Aware Physical Design and Run-Time Optimization for sub-10nm 2D and 3D Integrated Circuits
SHF:Small:10nm 以下 2D 和 3D 集成电路的电磁感知物理设计和运行时优化
- 批准号:
1816361 - 财政年份:2018
- 资助金额:
-- - 项目类别:
Standard Grant
SHF: Small: Physics-Based Electromigration Assessment and Validation For Reliability-Aware Design and Management
SHF:小型:基于物理的电迁移评估和验证,用于可靠性设计和管理
- 批准号:
1527324 - 财政年份:2015
- 资助金额:
-- - 项目类别:
Standard Grant
Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors
多核和 3D 微处理器的热敏系统级可靠性分析和管理
- 批准号:
1255899 - 财政年份:2013
- 资助金额:
-- - 项目类别:
Continuing Grant
US-Singapore Planning Visit: Collaborative Research on Design and Verification of 60Ghz RF/MM Integrated Circuits
美国-新加坡计划访问:60Ghz RF/MM 集成电路设计与验证合作研究
- 批准号:
1051797 - 财政年份:2011
- 资助金额:
-- - 项目类别:
Standard Grant
IRES: Development of Global Scientists and Engineers by Collaborative Research on Variation-Aware Nanometer IC Design
IRES:通过变异感知纳米 IC 设计的合作研究来促进全球科学家和工程师的发展
- 批准号:
1130402 - 财政年份:2011
- 资助金额:
-- - 项目类别:
Standard Grant
SHF: Small: Variational and Bound Performance Analysis of Nanometer Mixed-Signal/Analog Circuits
SHF:小型:纳米混合信号/模拟电路的变分和束缚性能分析
- 批准号:
1116882 - 财政年份:2011
- 资助金额:
-- - 项目类别:
Standard Grant
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