SHF: Small: Physics-Based Electromigration Assessment and Validation For Reliability-Aware Design and Management

长期可靠性已成为当今计算机和智能手机中使用的集成电路（IC）芯片设计的重大挑战。在许多影响中，由于积极的晶体管缩放和增加的功率密度，电迁移引起的可靠性已成为主要的限制因素。在这个项目中，PI建议通过在电路级和系统级提供更准确的电迁移模型和评估技术来解决IC可靠性问题，以便在设计阶段和运行阶段充分考虑、利用和优化电迁移引起的可靠性和老化效应，以最小的设计成本提高芯片的可靠性和寿命。此外，通过与行业合作伙伴的合作，预计所提出的技术将影响设计和工具开发社区，从而提高设计生产力。该项目旨在开发新的基于物理学的电迁移模型和全芯片评估技术，在设计阶段进行模型验证以实现准确而有效的电迁移验证，并在纳米IC芯片运行时实施电迁移感知可靠性管理。首先，该研究将开发新的物理精确的电迁移模型，以更好地预测多分支互连树的平均故障时间，这在IC芯片中很常见，包括空洞成核和空洞生长阶段。其次，该项目将开发电迁移模型，可以适应随时间变化的温度和电流密度，这反映了一个更现实的芯片工作条件，由于单线和多分支互连树随时间变化的负载。除此之外，项目团队还将开发基于资源的电迁移模型，这些模型更适合系统级运行时可靠性优化和管理。

Long-term reliability has become a significant challenge for design of integrated circuit (IC) chips used in today's computers and smart phones. Among many effects, electromigration-induced reliability has become the dominant limiting factor due to aggressive transistor scaling and increasing power density. In this project, the PI proposes to address IC reliability problems by providing more accurate electromigration models and assessment techniques at both circuit level and system level so that electromigration induced reliability and aging effects can be fully accounted, leveraged and optimized at both the design stage and run time stage to improve chip reliability and their lifetime at minimum design costs. Furthermore, through the collaborations with the industry partners, the proposed techniques are expected to impact the design and tool development community, thus increasing design productivity. This project also enables the institution to hire students from underrepresented groups, thus enhancing the diversity of science and technology workforce.The project seeks to develop new physics-based electromigration models and full-chip assessment techniques, to perform model validation for accurate yet efficient electromigration verification at the design stage, and to enforce electromigration-aware reliability management at run time for nanometer IC chips. First, the research will develop new physics-accurate electromigration models to better predict mean time to failure for multi-branch interconnect trees, which are commonly seen in IC chips, for both void nucleation and void growth phases. Second, the project will develop electromigration models that can accommodate time-varying temperature and current densities, which reflect a more realistic chip working condition due to time-varying loads for both single wire and multi-branch interconnect trees. On top of this, the project team will develop resource-based electromigration models, which are more amenable to the system-level run-time reliability optimization and management.