IRES: Development of Global Scientists and Engineers by Collaborative Research on Variation-Aware Nanometer IC Design

该项目将为美国学生提供在验证和设计纳米硅基纳米集成计算和通信系统方面获得国际研究经验的机会。美国学生每年将在中国北京的清华大学学习四周。该项目将支持加州大学滨江分校MSLAB实验室和清华大学设计自动化实验室（EDA）之间的合作研究和教育活动。 该团队将共同应对验证和设计硅基纳米超大规模集成电路系统的挑战。 合作研究项目将集中在有效的统计全芯片功率估计，考虑工艺变化与空间相关性和芯片良率提高技术，由于功率和时序变化。美国学生将共同开发新的统计泄漏、动态和总功率估计技术以及统计芯片成品率优化技术，用于纳米高性能集成计算和通信系统的设计和优化。拟议的合作教育和研究活动将为美国学生提供独特的培训，指导，网络和智力发展机会。这种国际参与将有利于学生的整个职业生涯，并有助于提高他们作为科学家和工程师的竞争力和能力。 最后，联合研究将加强现有的计算机工程研究和教育计划，并扩大合作研究工作在加州大学滨江协同一个公认的和资助的研究计划在中国。 课程和教科书的开发将推动超大规模集成电路设计技术的研究在加州大学滨江和促进统计超大规模集成电路性能建模和评估领域作为一个学术学科。

This project will provide U.S. students with the opportunity to gain international research experience in verifying and designing nanometer silicon-based nanometer integrated computing and communication systems. U.S. students will spend four weeks per year at Tsinghua University in Beijing, China. This project will support the collaborative research and education activities between the MSLAB Lab at University of California at Riverside and the Design Automation Lab (EDA) at Tsinghua University of China. The team will jointly tackle the challenges of verifying and designing silicon-based nanometer VLSI systems. The collaborative research projects will focus on the efficient statistical full-chip power estimation considering process variations with spatial correlations and chip yield improvement techniques due to power and timing variations. U.S. students will jointly develop new statistical leakage, dynamic and total power estimation techniques and statistical chip yield optimization techniques for design and optimization of nanometer high performance integrated computing and communication systems.Broader Impact. The proposed collaborative educational and research activities will provide unique training, mentoring, networking and intellectual development opportunities for U.S. students. Such international engagement will benefit the students' entire careers and help improve their competitiveness and competency as scientists and engineers. Finally, the joint research will strengthen existing computer engineering research and education programs, and broaden the collaborative research works at UC Riverside in synergy with one well-recognized and funded research program in China. The curriculum and textbook development will boost the VLSI design technique research at UC Riverside and promote the statistical VLSI performance modeling and estimation field as a scholarly discipline.