IRES: Development of Global Scientists and Engineers by Collaborative Research on Variation-Aware Nanometer IC Design

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This project will provide U.S. students with the opportunity to gain international research experience in verifying and designing nanometer silicon-based nanometer integrated computing and communication systems. U.S. students will spend four weeks per year at Tsinghua University in Beijing, China. This project will support the collaborative research and education activities between the MSLAB Lab at University of California at Riverside and the Design Automation Lab (EDA) at Tsinghua University of China. The team will jointly tackle the challenges of verifying and designing silicon-based nanometer VLSI systems. The collaborative research projects will focus on the efficient statistical full-chip power estimation considering process variations with spatial correlations and chip yield improvement techniques due to power and timing variations. U.S. students will jointly develop new statistical leakage, dynamic and total power estimation techniques and statistical chip yield optimization techniques for design and optimization of nanometer high performance integrated computing and communication systems.Broader Impact. The proposed collaborative educational and research activities will provide unique training, mentoring, networking and intellectual development opportunities for U.S. students. Such international engagement will benefit the students' entire careers and help improve their competitiveness and competency as scientists and engineers. Finally, the joint research will strengthen existing computer engineering research and education programs, and broaden the collaborative research works at UC Riverside in synergy with one well-recognized and funded research program in China. The curriculum and textbook development will boost the VLSI design technique research at UC Riverside and promote the statistical VLSI performance modeling and estimation field as a scholarly discipline.