A CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS Devices

0541465加州大学圣巴巴拉分校的Banerjee，Kaustavu非经典cmos器件多尺度电热建模与仿真的CAD框架随着cmos器件在90 nm节点以外的扩展有增无减，包括严重的短沟道效应、不断增加的漏电流和功耗在内的许多关键挑战正在加速引入新的材料和器件结构，以将cmos的寿命延长到甚至可能超过22 nm节点。这些器件被归类为非经典CMOS器件，包括应变硅、超薄体绝缘硅(UTB-SOI)、双栅(如FinFET)和多栅器件。虽然这些器件结构试图解决上述缩放挑战，但这些超大规模器件中的热管理越来越受到关注，因为引入了导热系数较低的材料(SOI，SiGe)和器件几何形状的物理限制。此外，对于声子的平均自由程与器件尺寸(沟道长度)相当(或大于)的器件几何结构，经典的漂移扩散理论无法准确预测晶体管沟道区的温度分布。目前，广泛用于器件级电热模拟的CAD工具使用漂移扩散或流体动力学模型以及假定局部热力学平衡的能量平衡方程，因此不能考虑这些影响，从而影响基于这些器件的集成电路的性能和可靠性。此外，还没有定义明确的方法来组合不同长度尺度的电热模型(根据CMOS晶体管的需要)，并随后生成准确的紧凑模型以实现快速电热模拟。此外，这些新兴的CMOS器件缺乏热管理还可能导致可靠性问题的显著增加，如静电放电(ESD)，这是半导体行业中所有IC故障的最大单一原因。因此，迫切需要开发合适的CAD框架来进行精确的多尺度电热建模和仿真，以便了解热效应对这些非经典器件的电特性以及随后对其电路性能和可靠性的影响。该框架对于优化这些器件的设计和了解各种电热权衡也是至关重要的。PI计划开发必要的CAD框架，以实现针对超大规模非经典CMOS器件的多尺度电热建模和仿真能力。这项研究涉及一种独特的方法，它结合了涉及电子-声子玻尔兹曼输运方程(BTE)的小规模亚连续电热模拟方法和基于宏观热扩散的方法。为了解决晶体管高场(漏)区附近声子输运的非局域性，需要进行小规模的模拟，并涉及电子-BTE和声子-BTE的自洽解，以便沿器件沟道产生准确的热流密度和热分布。接下来，通过将这些模拟的结果与经典的热扩散方法的结果(对于晶体管的其他区域)相结合，PI将为各种电热量(包括热阻、热电容和热时间常数)开发精确的物理和紧凑的模型，作为器件材料、工艺和偏置条件以及器件几何的函数。这些紧凑的模型将被用来使用SPICE进行快速的稳态和暂态电热模拟，从而分析和优化各种晶体管结构。最重要的是，由于性能和功耗严重依赖于热特性，电热CAD框架将用于设计热感知电路，以便从它们中获得最大效益，并进行各种电-热权衡。此外，PI将研究对ESD保护电路的影响，以了解高电流条件下的电热行为，并优化器件设计以提高ESD可靠性。整个计划还将研究与所有级别的教育(K-12、本科生、研究生、继续教育)联系起来，部分是通过参与由教育专业人员设计的计划。作为加州纳米系统研究所(CNSI)的附属教员，PI计划参加由CNSI赞助的各种外展活动，以及UCSB材料研究实验室(MRL)和纳米技术(NNIN)提供的活动，包括学生和教师研究培训实习计划。此外，该项目还将重点放在招募和留住未被充分代表的群体进入纳米科学和工程。

0541465Banerjee, KaustavU of Cal Santa BarbaraA CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS DevicesAs scaling of CMOS devices continues unabated beyond the 90 nm node, a number of critical challenges including severe short-channel effects, increasing leakage currents and power dissipation are accelerating the introduction of new materials and device structures to extend the lifetime of CMOS down to, and perhaps beyond the 22 nm node. These devices are classified as non-classical CMOS and include strained-Si, ultra-thin body Silicon-on-Insulator (UTB-SOI), double-gate (such as FinFETs) and multi-gate devices. While these device structures seek to address the above mentioned scaling challenges, thermal management in these ultra scaled devices is an increasing concern made worse by the introduction of materials with poorer thermal conductivity (SOI, SiGe) and the physical confinement of the device geometries. Moreover, for device geometries where the mean free path of the phonons are comparable to (or larger than) the device size (channel length), classical drift-diffusion theory fails to accurately predict the temperature profile in the channel region of the transistors. At present, CAD tools that are widely used for device level electrothermal simulations, use drift-diffusion or hydrodynamic models and energy-balance equations assuming local thermodynamic equilibrium and therefore do not account for these effects, thereby compromising the performance and reliability of integrated circuits based on these devices. Moreover, there is no well defined methodology that combines electrothermal models at different length scales (as needed for a CMOS transistor) and subsequently generates accurate compact models to allow fast electrothermal simulations. Additionally, lack of thermal management in these emerging CMOS devices can also lead to significant increase in reliability problems such as electrostatic discharge (ESD), which is known to be the largest single cause of all IC failures in the semiconductor industry. Hence, there is an imminent need for developing suitable CAD framework for accurate multi-scale electrothermal modeling and simulation, in order to understand the impact of thermal effects on the electrical characteristics of these non-classical devices and subsequently on their circuit performance and reliability. The framework is also critical for optimizing the design of these devices and to understand various electrical-thermal tradeoffs.The PI plans to develop the necessary CAD framework to enable multi-scale electrothermal modeling and simulation capabilities for ultra-scaled non-classical CMOS devices. The research involves a unique approach that combines a small-scale sub-continuum electrothermal simulation methodology involving the electron-phonon Boltzmann Transport Equations (BTE) with a macro-scale heat-diffusion based methodology. The small-scale simulations are necessary to account for the non-locality of phonon transport near the high electric field (drain) region of the transistor and involve self-consistent solutions of the electron-BTE and the phonon-BTE to generate accurate heat flux and thermal profile along the channel of the device. Next, by coupling together the results of these simulations with the ones from classical heat-diffusion approach (for other areas of the transistors) the PI will develop accurate physical as well as compact models for various electrothermal quantities including thermal resistance, thermal capacitance and thermal time constant as a function of device materials, process and bias conditions, and device geometry. These compact models will then be used to carry out fast steady-state and transient electrothermal simulations using SPICE and thereby analyze and optimize various transistor architectures. Most importantly, since performance and power dissipation are critically dependent on the thermal profile, the electrothermal CAD framework will be used to design thermally-aware circuits so that maximum benefit can be derived from them and various electrical-thermal tradeoffs can be carried out. Additionally, the PI will study implications for ESD protection circuitsunderstand electrothermal behavior under high-current conditions and optimize device design for improving ESD reliability. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-ed) partly via participation in programs designed by education professionals. As an affiliated faculty of the California NanoSystems Institute (CNSI), the PI plans to participate in various outreach activities sponsored by the CNSI as well as those offered by the Materials Research Lab (MRL) and the Nanotech (NNIN) at UCSB including the student and teacher research training internship programs. Additionally, the project provides a substantial focus on recruitment and retention of underrepresented groups into nanoscience and engineering.