Optimization Schemes for Large Scale Digital Circuits in Presence of Fabrication Randomness

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Reduction in fabrication dimensions has resulted in significant increase in the randomness associated with the fabricated parameters of large scale digital circuits. This has begun to severely impact the manufacturing yield and therefore the profitability of the semiconductor industry. In this research the investigators are focusing on developing formal optimization schemes for synthesizing large scale digital circuits while proactively considering randomness induced yield loss as an optimization criteria.As a key intellectual merit, specific digital circuit optimization problem instances that can be modeled as convex programs are being investigated in presence of fabrication randomness. Using a sound mathematical understanding of the nature of the yield loss function, customized optimization algorithms are being developed. Some of these algorithms leverage the special mathematical structure of the problem instances (convexity of the yield loss function in some special cases). For such instances the investigators study modifications of formal convex optimization methods (like cutting plane/interior point etc.) for improving the rates of convergence. In cases where such mathematical properties do not exist, efficient heuristics are being developed. A key agenda under investigation is how should such optimization schemes be integrated with statistical estimation methods (which measure the yield loss for a specific solution instance and are known to be very slow). Improving the productivity and profitability of the semiconductor industry, improving the applicability of nanotechnology (where manufacturing randomness is a major concern) and improving the teaching infrastructure through graduate and undergraduate student training are key broad impacts of this work.