SGER: Lithography- Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs

摘要0634321 Ankur SrivastavaU的马里兰州-学院公园NSF-SGER：超大规模碳纳米管和石墨烯带嵌入CMOS数字集成电路的光刻约束分析纳米结构石墨（碳纳米管和/或石墨烯纳米带）具有非凡的性能（高载流子迁移率，可调带隙，高热导率，高电流容量，缺乏电迁移），这使得它成为解决CMOS中有源层和互连层中存在的问题的非常有前途的候选物。这项研究将研究在传统CMOS电路的有源层或互连层中嵌入纳米结构石墨。具体而言，我们将：（1）发展对CNT和石墨烯条带晶体管（纳米结构碳领域的新发明）的硅兼容制造工艺的良好理解，（2）发展用于预测直径、长度、取向、宽度等的可变性的概率模型，(3)使用该模型，我们将重新分析CNT晶体管和互连的潜在优点，并将它们与石墨烯条晶体管的优点进行比较。为此，我们将研究大规模CMOS晶体管组，电网网络，时钟树和全球总线（4）提供一套tolerance给工厂工程师，他们需要在他们的制造过程中实现有效开发嵌入到硅中的碳基纳米技术，和（5）开发一套设计规则，如果设计师遵循，将导致高度可制造的布局与两个CNT，石墨烯带和传统CMOS。我们的方法的关键新奇在于：a）我们将明确比较碳纳米管和石墨烯晶体管（纳米结构碳的一项新发明）B）我们将明确考虑现有技术制造工艺的实际限制（与不考虑这种缺陷的现有技术不同）c）我们将研究它们在大规模CMOS/CMOS上的适用性。互连结构，如晶体管组、时钟树、电源网格，等，而不是单独的晶体管和互连，因此考虑这些特定的大规模CMOS/互连结构所带来的挑战。利用来自真实的制造工艺和真实的实验器件的数据的艺术设计方法来解决在CMOS中并入石墨纳米结构的问题。该提案汇集了Srivastava在设计自动化和设计方法方面的专业知识，以及Fuhrer在碳纳米管和石墨烯器件方面的实验专业知识。首次将石墨烯条晶体管大规模应用于硅CMOS进行评估，并与传统的碳纳米管进行比较。更重要的是，这种评估将明确考虑晶圆厂的限制和缺陷。最后，我们将明确研究大规模结构，如电网、时钟树、晶体管组，并评估纳米结构碳的适用性，而不是专注于微尺度集成问题。更广泛的影响拟议的研究将奠定基础，为更大的研究纳入碳nanostructuresinto CMOS这将扩大到包括设备原型和设备级和系统级建模。拟议的研究将产生第一个现实的研究，将碳纳米结构的CMOS，并将有助于指导研究的最佳领域的探索interms的碳纳米结构的制造，组装和表征。碳纳米结构是将半导体技术路线图延伸到后硅时代的非常有前途的候选者。在这个时代，CMOS的持续扩展将产生巨大的经济和社会效益。教育影响拟议的研究将开始设计和纳米电子器件之间的合作对话。两名研究生将在纳米电子学研究的前沿接受跨学科培训。

ABSTRACT0634321Ankur SrivastavaU of Maryland - College ParkNSF-SGER: Lithography-Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs Nanostructure graphite (carbon nanotubes and/or graphene nanostrips) has extraordinary properties (highcarrier mobility, tunable bandgap, high thermal conductivity, high current capacity, lack ofelectromigration) that makes it a very promising candidate for solving existing problems in both the activelayer and interconnect layers in CMOS. The proposed research will study the embedding of nanostructuredgraphite in the active or interconnect layers of conventional CMOS circuits. Specifically, we will: (1)develop a sound understanding of the silicon compatible fabrication process of CNTs and graphene striptransistors (a new invention in the field of nanostructured carbon), (2) develop a probabilistic model forpredicting the variability in diameter, length, orientation, width etc., (3) using this model we will re-analyze the potential advantages of CNT transistors and interconnects and compare them with the advantages of graphene strip transistors. To this end we will study large scale CMOS transistor banks, power grid networks, clock trees and global busses (4) give a set of tolerences to fab-engineers which they need toachieve in their fabrication process for effective exploitation of carbon based nanotechnology embeddedinto silicon, and (5) develop a set of design rules which if the designers follow would result in a highlymanufacturable layouts with both CNTs, graphene strips and traditional CMOS. The key novelty of ourapproach is the fact that a) we will explicitly compare carbon nanotubes and graphene transistors (a newinvention in nanostructured carbon) b) we will explicitly consider the practical limitations of state of the art fabrication processes (unlike the current state of the art that does not take such imperfections into account) c) we will investigate their applicability on large scale CMOS/interconnect structures like transistor banks, clock trees, power grid meshes, etc rather than individual transistors and interconnects and therefore consider the challenges imposed by these specific large scale CMOS/interconnect structures.Intellectual Merit A significant intellectual merit of the proposal is the pairing of state-of-the-art design methodologies with data from real fabrication process and real experimental devices to tackle the problem of incorporation of graphite nanostructures in CMOS. This proposal brings together Srivastava with expertise in design automation and design methodologies, with Fuhrer, who has experimental expertise in carbon nanotube and graphene devices. For the first time large scale applicability of graphene strip transistors to silicon CMOS would be evaluated and compared with traditional carbon nanotubes. More so this evaluation would explicitly consider the fab limitations and imperfections. Finally, instead of focusing on micro scaleintegration problems, we will explicitly investigate large scale structures like power grids, clock trees,transistor banks and evaluate the applicability of nanostructured carbon. Such an analysis has not been donebefore.Broader ImpactsThe proposed research will lay the foundation for a larger study of incorporation of carbon nanostructuresinto CMOS which would be expended to include device prototyping and device-level and systems-levelmodeling. The proposed research will produce the first realistic studies of incorporating carbonnanostructures in CMOS, and will be instrumental in guiding research to the optimal areas of exploration interms of carbon nanostructure fabrication, assembly, and characterization. Carbon nanostructures are verypromising candidates for extending the semiconductor technology roadmap into the post-silicon era. Thecontinued scaling of CMOS in this era will have enormous economic and societal benefits.Educational ImpactThe proposed research will begin a collaborative dialog between the design and nanoelectronics devicecommunities. Two graduate students will receive interdisciplinary training at the forefront ofnanoelectronics research.