SGER: Lithography- Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs

摘要：ankur SrivastavaU， Maryland - College ParkNSF-SGER：纳米结构石墨（碳纳米管和/或石墨烯纳米带）具有非凡的性能（高载流子迁移率，可调带隙，高导热性，大电流容量，缺乏电迁移），使其成为解决CMOS中有源层和互连层存在的问题的非常有前途的候选者。该研究将研究在传统CMOS电路的有源层或互连层中嵌入纳米结构石墨。具体来说，我们将：(1)对碳纳米管和石墨烯带状晶体管（纳米结构碳领域的一项新发明）的硅兼容制造工艺有一个很好的理解，(2)开发一个概率模型来预测直径、长度、方向、宽度等的可变性，(3)使用这个模型我们将重新分析碳纳米管晶体管和互连的潜在优势，并将它们与石墨烯带状晶体管的优势进行比较。为此，我们将研究大规模CMOS晶体管组、电网网络、时钟树和全球总线(4)为晶圆厂工程师提供一套公差，他们需要在制造过程中实现这些公差，以便有效地利用嵌入硅中的碳基纳米技术；(5)制定一套设计规则，如果设计师遵循这些规则，将导致碳纳米管、石墨烯带和传统CMOS的高度可制造布局。我们方法的关键新颖之处在于，a)我们将明确比较碳纳米管和石墨烯晶体管（纳米结构碳中的一项新发明）b)我们将明确考虑最先进制造工艺的实际限制（不像目前的最先进技术没有考虑到这些缺陷）c)我们将研究它们在大规模CMOS/互连结构上的适用性，如晶体管组，时钟树，电网网格，等等，而不是单个晶体管和互连，因此考虑这些特定的大规模CMOS/互连结构所带来的挑战。该提案的一个重要的智力价值是将最先进的设计方法与实际制造过程和实际实验设备的数据相结合，以解决将石墨纳米结构整合到CMOS中的问题。该提案将Srivastava与Fuhrer结合在一起，Srivastava在设计自动化和设计方法方面具有专业知识，Fuhrer在碳纳米管和石墨烯器件方面具有实验专业知识。将首次评估石墨烯带状晶体管在硅CMOS上的大规模适用性，并与传统的碳纳米管进行比较。更重要的是，这种评估将明确考虑晶圆厂的限制和缺陷。最后，我们将明确研究大型结构，如电网、时钟树、晶体管库，并评估纳米结构碳的适用性，而不是专注于微观尺度的集成问题。这样的分析以前从未有人做过。更广泛的影响拟议的研究将为将碳纳米结构纳入CMOS的更大规模研究奠定基础，该研究将扩展到包括设备原型和设备级和系统级建模。该研究将产生将碳纳米结构整合到CMOS中的第一个现实研究，并将有助于指导研究探索碳纳米结构制造，组装和表征方面的最佳领域。碳纳米结构非常有希望将半导体技术路线图延伸到后硅时代。在这个时代，CMOS的持续规模化将带来巨大的经济和社会效益。教育影响提议的研究将开始设计和纳米电子器件社区之间的协作对话。两名研究生将接受纳米电子学研究前沿的跨学科培训。

ABSTRACT0634321Ankur SrivastavaU of Maryland - College ParkNSF-SGER: Lithography-Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs Nanostructure graphite (carbon nanotubes and/or graphene nanostrips) has extraordinary properties (highcarrier mobility, tunable bandgap, high thermal conductivity, high current capacity, lack ofelectromigration) that makes it a very promising candidate for solving existing problems in both the activelayer and interconnect layers in CMOS. The proposed research will study the embedding of nanostructuredgraphite in the active or interconnect layers of conventional CMOS circuits. Specifically, we will: (1)develop a sound understanding of the silicon compatible fabrication process of CNTs and graphene striptransistors (a new invention in the field of nanostructured carbon), (2) develop a probabilistic model forpredicting the variability in diameter, length, orientation, width etc., (3) using this model we will re-analyze the potential advantages of CNT transistors and interconnects and compare them with the advantages of graphene strip transistors. To this end we will study large scale CMOS transistor banks, power grid networks, clock trees and global busses (4) give a set of tolerences to fab-engineers which they need toachieve in their fabrication process for effective exploitation of carbon based nanotechnology embeddedinto silicon, and (5) develop a set of design rules which if the designers follow would result in a highlymanufacturable layouts with both CNTs, graphene strips and traditional CMOS. The key novelty of ourapproach is the fact that a) we will explicitly compare carbon nanotubes and graphene transistors (a newinvention in nanostructured carbon) b) we will explicitly consider the practical limitations of state of the art fabrication processes (unlike the current state of the art that does not take such imperfections into account) c) we will investigate their applicability on large scale CMOS/interconnect structures like transistor banks, clock trees, power grid meshes, etc rather than individual transistors and interconnects and therefore consider the challenges imposed by these specific large scale CMOS/interconnect structures.Intellectual Merit A significant intellectual merit of the proposal is the pairing of state-of-the-art design methodologies with data from real fabrication process and real experimental devices to tackle the problem of incorporation of graphite nanostructures in CMOS. This proposal brings together Srivastava with expertise in design automation and design methodologies, with Fuhrer, who has experimental expertise in carbon nanotube and graphene devices. For the first time large scale applicability of graphene strip transistors to silicon CMOS would be evaluated and compared with traditional carbon nanotubes. More so this evaluation would explicitly consider the fab limitations and imperfections. Finally, instead of focusing on micro scaleintegration problems, we will explicitly investigate large scale structures like power grids, clock trees,transistor banks and evaluate the applicability of nanostructured carbon. Such an analysis has not been donebefore.Broader ImpactsThe proposed research will lay the foundation for a larger study of incorporation of carbon nanostructuresinto CMOS which would be expended to include device prototyping and device-level and systems-levelmodeling. The proposed research will produce the first realistic studies of incorporating carbonnanostructures in CMOS, and will be instrumental in guiding research to the optimal areas of exploration interms of carbon nanostructure fabrication, assembly, and characterization. Carbon nanostructures are verypromising candidates for extending the semiconductor technology roadmap into the post-silicon era. Thecontinued scaling of CMOS in this era will have enormous economic and societal benefits.Educational ImpactThe proposed research will begin a collaborative dialog between the design and nanoelectronics devicecommunities. Two graduate students will receive interdisciplinary training at the forefront ofnanoelectronics research.