SGER: Lithography- Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs

Ankur SriastavaU of Marland-College ParkNSF-SGER：超大规模碳纳米管和石墨烯条带嵌入式CMOS数字集成电路的光刻约束分析石墨(碳纳米管和/或石墨烯纳米带)纳米结构石墨(碳纳米管和/或石墨烯纳米带)具有非凡的性能(高载流子迁移率、可调谐带隙、高导热系数、高电流容量、缺乏电迁移)，这使其成为解决CMOS有源层和互连层中现有问题的非常有前途的候选材料。这项研究将研究将纳米结构的石墨嵌入到传统CMOS电路的有源层或互连层中。具体地说，我们将：(1)对碳纳米管和石墨烯条带晶体管(纳米结构碳领域的一项新发明)的硅兼容制造工艺有一个良好的理解，(2)开发一个概率模型来预测直径、长度、取向、宽度等方面的变化，(3)利用这个模型，我们将重新分析碳纳米管和互连的潜在优势，并将它们与石墨烯条带晶体管的优势进行比较。为此，我们将研究大规模的CMOS晶体管组、电网网络、时钟树和全球总线(4)为制造工程师提供他们在制造过程中需要达到的一组公差，以便有效地利用嵌入到硅中的碳基纳米技术，以及(5)开发一套设计规则，如果设计者遵循这些规则，将产生具有碳纳米管、石墨烯条带和传统CMOS的高度可制造的版图。该方法的主要新奇之处在于a)我们将明确地比较碳纳米管和石墨烯晶体管(纳米结构碳中的一项新发明)b)我们将明确地考虑现有制造工艺的实际限制(不同于不考虑这些缺陷的当前技术状态)c)我们将调查它们在诸如晶体管组、时钟树、电源网格之类的大规模CMOS/互连结构上的适用性，这项提议的一个显著的智力优点是将最先进的设计方法与来自实际制造工艺和真实实验设备的数据配对，以解决将石墨纳米结构纳入到CMOS中的问题。这项提议将在设计自动化和设计方法方面拥有专业知识的Sriastava与在碳纳米管和石墨烯设备方面拥有实验专业知识的Fuhrer结合在一起。首次评估了石墨烯条状晶体管在硅CMOS中的大规模适用性，并将其与传统的碳纳米管进行了比较。更重要的是，这项评估将明确考虑制造厂的局限性和缺陷。最后，我们将明确研究电网、时钟树、晶体管存储体等大规模结构，并评估纳米结构碳的适用性，而不是关注微观集成问题。这项研究将为更大范围的将碳纳米结构融入到CMOS中的研究奠定基础，该研究将扩展到包括器件原型和器件级和系统级建模。这项拟议的研究将产生第一个将碳结构纳入到CMOS中的现实研究，并将有助于指导研究向碳纳米结构制造、组装和表征等最佳探索领域发展。碳纳米结构是将半导体技术路线图扩展到后硅时代的非常有前途的候选者。在这个时代，不断扩大CMOS的规模将产生巨大的经济和社会效益。教育影响拟议中的研究将开始设计和纳米电子设备社区之间的合作对话。两名研究生将在纳米电子学研究的前沿接受跨学科培训。

ABSTRACT0634321Ankur SrivastavaU of Maryland - College ParkNSF-SGER: Lithography-Constrained Analysis of Very Large Scale Carbon Nanotube and Graphene Strip Embedded CMOS Digital ICs Nanostructure graphite (carbon nanotubes and/or graphene nanostrips) has extraordinary properties (highcarrier mobility, tunable bandgap, high thermal conductivity, high current capacity, lack ofelectromigration) that makes it a very promising candidate for solving existing problems in both the activelayer and interconnect layers in CMOS. The proposed research will study the embedding of nanostructuredgraphite in the active or interconnect layers of conventional CMOS circuits. Specifically, we will: (1)develop a sound understanding of the silicon compatible fabrication process of CNTs and graphene striptransistors (a new invention in the field of nanostructured carbon), (2) develop a probabilistic model forpredicting the variability in diameter, length, orientation, width etc., (3) using this model we will re-analyze the potential advantages of CNT transistors and interconnects and compare them with the advantages of graphene strip transistors. To this end we will study large scale CMOS transistor banks, power grid networks, clock trees and global busses (4) give a set of tolerences to fab-engineers which they need toachieve in their fabrication process for effective exploitation of carbon based nanotechnology embeddedinto silicon, and (5) develop a set of design rules which if the designers follow would result in a highlymanufacturable layouts with both CNTs, graphene strips and traditional CMOS. The key novelty of ourapproach is the fact that a) we will explicitly compare carbon nanotubes and graphene transistors (a newinvention in nanostructured carbon) b) we will explicitly consider the practical limitations of state of the art fabrication processes (unlike the current state of the art that does not take such imperfections into account) c) we will investigate their applicability on large scale CMOS/interconnect structures like transistor banks, clock trees, power grid meshes, etc rather than individual transistors and interconnects and therefore consider the challenges imposed by these specific large scale CMOS/interconnect structures.Intellectual Merit A significant intellectual merit of the proposal is the pairing of state-of-the-art design methodologies with data from real fabrication process and real experimental devices to tackle the problem of incorporation of graphite nanostructures in CMOS. This proposal brings together Srivastava with expertise in design automation and design methodologies, with Fuhrer, who has experimental expertise in carbon nanotube and graphene devices. For the first time large scale applicability of graphene strip transistors to silicon CMOS would be evaluated and compared with traditional carbon nanotubes. More so this evaluation would explicitly consider the fab limitations and imperfections. Finally, instead of focusing on micro scaleintegration problems, we will explicitly investigate large scale structures like power grids, clock trees,transistor banks and evaluate the applicability of nanostructured carbon. Such an analysis has not been donebefore.Broader ImpactsThe proposed research will lay the foundation for a larger study of incorporation of carbon nanostructuresinto CMOS which would be expended to include device prototyping and device-level and systems-levelmodeling. The proposed research will produce the first realistic studies of incorporating carbonnanostructures in CMOS, and will be instrumental in guiding research to the optimal areas of exploration interms of carbon nanostructure fabrication, assembly, and characterization. Carbon nanostructures are verypromising candidates for extending the semiconductor technology roadmap into the post-silicon era. Thecontinued scaling of CMOS in this era will have enormous economic and societal benefits.Educational ImpactThe proposed research will begin a collaborative dialog between the design and nanoelectronics devicecommunities. Two graduate students will receive interdisciplinary training at the forefront ofnanoelectronics research.