SGER: Design Technologies for Nanoscale VLSI

SGER：纳米级 VLSI 设计技术

• 批准号: 0739623
• 负责人: Marios Papaefthymiou
• 金额: $ 15万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-09-15 至 2009-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0739623&HistoricalAwards=false
• 关键词: SGER; Design; Technologies; Nanoscale; VLSI

ABSTRACT0739623Marios C. PapaefthymiouUniversity of MichiganIntellectual MeritThe continuing scaling of semiconductor process technology brings about new challenges in the designof VLSI systems, while at the same time motivating new approaches for addressing them. Power density inhigh-end integrated systems has already reached performance-limiting levels. Increased device variabilityresults in greater delay uncertainty, dictating the use of larger design margins and further limiting performance. Yet, silicon per device continues to decrease at exponential rates, enabling novel uses of siliconarea. This research project will investigate next-generation design technologies for the realization of nanoscale VLSI systems in silicon. Specifically, this project will focus on the exploration of so-called charge recovery design technologies that enable operation at new levels of power-efficiency while reducing uncertainty due to device variability. In conventional VLSI design, capacitors are switched abruptly between supply and ground, experiencing high peak currents and dissipating all their stored energy as heat across resistive devices. Furthermore, device variability leads to significant uncertainty in the clock arrival times of conventional distribution networks with buffers. In contrast to conventional integrated systems, charge-recovery designs switch capacitors gradually, maintaining low peak currents and returning any undissipated energy back to the power supply. Therefore, charge-recovery designs can potentially lead to substantial reductions in switching power and gate leakage. Moreover, since they rely on buffer-less resonant clock distribution networks, charge-recovery designs are also expected to yield substantial reductions in clock delay uncertainty. The significant potential of charge recovery has so far remained untapped, as it represents a departure from established design practices. The main objective of this project is to explore and assess the potential of charge-recovery technologies, including circuitry, design methodologies, and computing architectures for realizing nanoscale silicon-based VLSI systems with unprecedented levels of power efficiency and performance. Broader ImpactsThe proposed research is expected to have a significant impact on the realization of next-generation VLSIsystems, promoting discovery, teaching, and learning in novel design technologies that address key issues innanoscale process nodes. Broader outcomes of the proposed effort include the integration of research activitiesinto graduate-level courses, the development of lectures and projects for advanced undergraduate-levelcourses, as well as the direct involvement of electrical engineering and computer science majors throughsenior-level design projects. Consistent with the PI's proven record in promoting broad participation, theproposed research and education activities will include participants from underrepresented groups.A1

半导体制程技术的持续规模化给VLSI系统的设计带来了新的挑战，同时也激发了解决这些挑战的新方法。高端集成系统的功率密度已经达到了性能极限。增加的器件可变性导致更大的延迟不确定性，决定使用更大的设计余量并进一步限制性能。然而，每个器件的硅继续以指数速率下降，使硅面积的新用途成为可能。该研究项目将研究在硅中实现纳米级超大规模集成电路系统的下一代设计技术。具体来说，该项目将专注于探索所谓的电荷回收设计技术，使其能够在新的能效水平上运行，同时减少设备可变性带来的不确定性。在传统的超大规模集成电路设计中，电容器在电源和地之间突然切换，经历峰值电流，并将其存储的所有能量作为热量散发到电阻器件上。此外，设备的可变性导致带缓冲的传统配电网时钟到达时间的显著不确定性。与传统的集成系统相比，电荷恢复设计逐渐开关电容器，保持低峰值电流，并将任何未耗散的能量返回给电源。因此，电荷恢复设计可以潜在地导致开关功率和栅极泄漏的大幅降低。此外，由于它们依赖于无缓冲谐振时钟分配网络，电荷恢复设计也有望大幅降低时钟延迟的不确定性。到目前为止，电荷回收的巨大潜力尚未开发，因为它代表了与既定设计实践的背离。该项目的主要目标是探索和评估电荷回收技术的潜力，包括电路、设计方法和计算架构，以实现具有前所未有的功率效率和性能水平的纳米级硅基VLSI系统。更广泛的影响拟议的研究预计将对下一代超大规模集成电路系统的实现产生重大影响，促进新设计技术的发现、教学和学习，解决纳米级工艺节点的关键问题。更广泛的成果包括将研究活动整合到研究生课程中，为高级本科课程开发讲座和项目，以及让电气工程和计算机科学专业的学生直接参与高级设计项目。与PI在促进广泛参与方面的良好记录一致，拟议的研究和教育活动将包括来自代表性不足的群体的参与者。A1