An Integrated Design and CAD Approach for Efficient Power Delivery in Multicore Processors

用于实现多核处理器高效供电的集成设计和 CAD 方法

• 批准号: 0903427
• 负责人: Sachin Sapatnekar
• 金额: $ 42万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-15 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0903427&HistoricalAwards=false
• 关键词: Integrated; Design; CAD; Approach; Efficient

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).The objective of this research is to develop solutions that ensure reliable power delivery in high-performance multicore systems. Technology trends for multicore chips show increased on-chip noise sources, decreasing supply voltage levels, and reduced headroom for noise: together these make the problem of on-chip power supply noise, which can cause a circuit to be nonfunctional, acutely difficult. The approach is based on an integrated strategy that incorporates novel design techniques, bolstered by computer-aided design (CAD) strategies to build reliable on-chip power distribution systems.The design thrust of the project will develop novel multicore-specific circuits, including switched decoupling capacitor (decap) circuits and active decaps, to actively cancel the supply noise in cores that suffer from large switching current. The modeling and CAD aspects will focus on analyzing multicore power grids containing a mix of these novel structures and traditional methods, and optimizing these grids using pre-silicon. Additionally, the PIs will develop CAD techniques to build adaptive structures into the circuit in the pre-silicon phase, in order to enable sensor-driven adaptive post-silicon power grid noise mitigation.Solutions from this research will facilitate the design of next-generation high-performance, low-voltage systems for computing and communication applications, and will be demonstrated on prototype implementations. The PIs plan to transfer technology through direct industrial collaborations, particularly leveraging this project's connections with the Semiconductor Research Corporation. The PIs will proactively recruit and nurture students from under-represented groups and develop new course materials for the undergraduate and graduate curriculum in the areas of electronics, chip design, and CAD.

该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的。这项研究的目标是开发解决方案，确保高性能多核系统的可靠供电。 多核芯片的技术趋势表明，片内噪声源增加，电源电压水平降低，噪声裕量减少：这些因素共同导致片内电源噪声问题变得非常困难，这可能导致电路无法正常工作。该方法是基于一个集成的策略，结合新的设计技术，由计算机辅助设计（CAD）策略支持，以建立可靠的片上电源分配系统。该项目的设计重点将开发新的多核心特定的电路，包括开关去耦电容（decap）电路和有源decap，以主动消除电源噪声的核心，遭受大开关电流。 建模和CAD方面将侧重于分析包含这些新结构和传统方法的混合的多核电网，并使用预硅优化这些电网。 此外，PI将开发CAD技术，在硅化前阶段将自适应结构构建到电路中，以实现传感器驱动的自适应硅化后电网噪声缓解。这项研究的解决方案将促进下一代高性能、低电压系统的设计，用于计算和通信应用，并将在原型实现中进行演示。PI计划通过直接的工业合作转移技术，特别是利用该项目与半导体研究公司的联系。PI将积极招募和培养来自代表性不足群体的学生，并为电子，芯片设计和CAD领域的本科生和研究生课程开发新的课程材料。