SHF: Small: Stress Management in Integrated Circuits

速度和功率是数字电子集成电路的关键属性，可转化为系统级指标，如电子系统中的响应时间和电池寿命。随着技术的进步，这些性能参数越来越依赖于系统中的热应力和机械应力。这种应力可能是有意引入的（固有应力）以提高电路性能，也可能是由于设计因素或由于电路中单个晶体管所面临的环境而无意引入的（外在应力）。本提案的目标是通过开发(a)快速建模方法(b)调用建模解决方案的优化技术，使系统和科学的方法能够在存在应力的情况下进行全芯片性能分析和优化。目前的应力建模技术表明，对应力效应进行全芯片分析的重要方法很少，而且很少以系统的方式进行应力优化。该项目将开发新的分析和半分析建模技术，这些技术具有计算效率和可扩展性，允许对常见结构进行快速分析。该方法将利用应力分析框架工具箱，将其调整为芯片环境并寻求新的效率。全芯片分析将通过调用设计的关键部分的建模技术来确定时间和功率的漂移。该项目将在硅前阶段和硅后阶段进行应力优化。该项目的研究目标将由教育努力和向工业转让技术的努力加以补充。

Speed and power are key attributes of a digital electronic integrated circuit that translate to system-level metrics such as response times and battery life in electronic systems. With progress in technology, these performance parameters are found to be increasingly dependent on thermal and mechanical stress in the system. This stress may be intentionally introduced (intrinsic stress) to enhance circuit performance, or may be unintentional (extrinsic stress) due to design factors or due to the environment faced by individual transistors in the circuit. The goal of this proposal is to enable a systematic and scientific approach to full-chip performance analysis and optimization in the presence of stress, through the development of (a) fast modeling approaches (b) optimization techniques that invoke the modeling solutions. The current state of the art in stress modeling shows few to no significant approaches for full-chip analysis of stress effects, and stress optimization is rarely performed in a systematic way. This project will develop novel analytical and semi-analytical modeling techniques that are computationally efficient and scalable, permitting fast analysis of commonly encountered structures. The approach will draw upon a toolbox of stress analysis frameworks, tailoring them to on-chip environments and seeking new efficiencies. Full-chip analysis will be performed by invoking the modeling techniques on critical segments of the design to determine the drift in timing and power. The project will perform stress optimization at both the pre-silicon stage and the post-silicon stage. The research goals of the project will be supplemented by educational efforts as well as technology transfer efforts to industry.