SHF: Medium: Collaborative Research: AgELESS: Aging Estimation and Lifetime Enhancement in Silicon Systems

SHF：媒介：合作研究：AgELESS：硅系统中的老化估计和寿命增强

• 批准号: 1162267
• 负责人: Sachin Sapatnekar
• 金额: $ 56万
• 依托单位: University of Minnesota-Twin Cities
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-05-01 至 2017-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1162267&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; AgELESS

As CMOS technologies scale down to smaller geometries, integrated circuits become more sensitive to aging-driven variations. Such variations can cause a manufactured part to become unreliable in the field over a period of time due to aging-induced circuit failures. To guard against this problem, it is essential to build design-time and run-time techniques that can model and optimize CMOS circuits. The AgELESS project brings together expertise in circuit design, computer-aided design, and test techniques, which together are expected to provide a more complete set of solutions to the overcome the reliability hurdle. This work explores several major aging-related failures, and develops a toolbox of techniques that can be used to enhance circuit reliability, while ensuring that the circuit meets all specifications on power/energy and performance. While AgELESS will not make a circuit ageless, it is expected to ensure that it will age less. The techniques developed in this research will be applicable to a range of applications of interest to the semiconductor industry, including enterprise-class for high-end computing systems, mobile and wireless communication applications, and embedded electronics, and will be made available to industry through multiple avenues, including industrial collaborations and active dissemination of research results. The educational impact of this project will involve new course materials on reliability for the undergraduate and graduate curriculum, and will train future scientists/engineers to learn creative problem-solving skills.

随着CMOS技术缩小到更小的几何尺寸，集成电路对老化驱动的变化变得更加敏感。 由于老化引起的电路故障，这种变化可能导致制造的部件在一段时间内在现场变得不可靠。 为了防止这个问题，它是必不可少的，以建立设计时和运行时的技术，可以建模和优化CMOS电路。 AgELESS项目汇集了电路设计、计算机辅助设计和测试技术方面的专业知识，预计将为克服可靠性障碍提供一套更完整的解决方案。这项工作探讨了几个主要的老化相关的故障，并开发了一个工具箱的技术，可用于提高电路的可靠性，同时确保电路满足所有规格的功率/能量和性能。虽然AgELESS不会使电路不老化，但预计它会确保它的老化程度更低。 本研究开发的技术将适用于半导体行业感兴趣的一系列应用，包括企业级高端计算系统、移动的和无线通信应用以及嵌入式电子产品，并将通过多种途径（包括工业合作和积极传播研究成果）提供给行业。该项目的教育影响将涉及本科生和研究生课程中关于可靠性的新教材，并将培训未来的科学家/工程师学习创造性解决问题的技能。