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SHF: Small: Enchancing the Reliability of Mixed-Signal Integrated Circuits

SHF：小型：提高混合信号集成电路的可靠性

基本信息

批准号：
1714805
负责人：
Sachin Sapatnekar
金额：
$ 45万
依托单位：
University of Minnesota-Twin Cities
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2017
资助国家：
美国
起止时间：
2017-09-01 至 2022-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1714805&HistoricalAwards=false
关键词：
SHF Small Enchancing Reliability Mixed

项目摘要

Silicon-based integrated circuit technologies, both at the cutting edge today and those that are predicted to emerge in the future, are based on the use of three-dimensional transistor structures with multiple gates, such as finFETs, trigate transistors, or gate-all-around devices. The semiconductor industry faces a new set of challenges with these structures, particularly in relation to reliability and failures. This project will research effective solutions to overcome these challenges so as to facilitate the design of the next generation of high-performance integrated circuits. In addition to research, the project has an educational component that includes the development of instructional material for the undergraduate and graduate curriculum on reliability in mixed-signal circuits, and in training future scientists/engineers to learn creative problem solving skills.Specifically, this project addresses the use of multigate transistor technologies in the design of mixed-signal integrated circuits with both digital and analog parts, using the case of input/output (I/O) circuits as a testbed for evaluating a set of proposed approaches that proactively model and mitigate circuit aging in transistors and interconnect wires. Specific aging mechanisms that will be investigated include bias temperature instability, hot carrier injection, gate oxide breakdown, and electromigration. These effects are accentuated by the increased thermal effects and thermal nonuniformities seen in multigate transistor technologies, and it is important to develop methods that tightly integrate reliability computations with thermal analysis. The work will link the impact of such effects at the transistor level to the mixed-signal block level, and then up to the system level. The proposed techniques will act in conjunction with on-chip compensation techniques that make circuits more robust to aging-induced performance drifts.

基于硅的集成电路技术，无论是今天的尖端技术，还是预计将在未来出现的技术，都是基于具有多个栅极的三维晶体管结构的使用，例如FinFET、触发器晶体管或栅极全能器件。半导体行业在这些结构上面临着一系列新的挑战，特别是在可靠性和故障方面。本项目将研究有效的解决方案来克服这些挑战，以促进下一代高性能集成电路的设计。除了研究，该项目还有一个教育部分，包括为本科生和研究生课程开发混合信号电路可靠性的教材，以及培训未来的科学家/工程师学习创造性的解决问题的技能。具体地说，该项目研究了多门晶体管技术在包含数字和模拟部件的混合信号集成电路设计中的使用，以输入/输出(I/O)电路为例来评估一套拟议的方法，这些方法主动建模并缓解晶体管和互连线中的电路老化。将研究的具体老化机制包括偏置温度不稳定性、热载流子注入、栅氧化物击穿和电迁移。多栅晶体管技术中增加的热效应和热不均匀加剧了这些影响，开发将可靠性计算与热分析紧密结合的方法是很重要的。这项工作将把这种效应在晶体管级别的影响连接到混合信号块级别，然后再向上连接到系统级别。建议的技术将与片上补偿技术相结合，使电路对老化引起的性能漂移更加稳健。

项目成果

期刊论文数量（8）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks

DOI：
10.1145/3394885.3431583
发表时间：
2020-09
期刊：
2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC)
影响因子：
0
作者：
V. A. Chhabria;V. Ahuja;Ashwath Prabhu;Nikhil Patil;Palkesh Jain;S. Sapatnekar
通讯作者：
V. A. Chhabria;V. Ahuja;Ashwath Prabhu;Nikhil Patil;Palkesh Jain;S. Sapatnekar

Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation

HCI 和 BTI 退化下延迟锁相环的可靠性分析