Offchip Interconnect Signaling Scheme with Near Zero Simultaneous Switching Noise

本研究的目的是开发一种信号方案，产生近零的同时开关噪声的I/O电路在封装或印刷电路板开关。在目前的封装和印刷电路板中，这是由由于返回路径不连续性而在电源层和接地层之间产生的空腔谐振引起的。该方法是使用在源处匹配的传输线来替换电源层，从而导致不间断的电流返回路径。这种方法可以应用于2D和3D集成系统。智能优点：当今的电子系统使用低阻抗配电网络。与这种做法相反，高阻抗传输线可以用来供电，从而消除了对数百个电容器的需要。使用建议的互连拓扑结构，预计在封装铜线将足以实现1.6TBps或更好的带宽之间的多核处理器和memory.Broader影响：高风险，影响深远的方法，在这个程序中调查是超出了电子行业的当前焦点，因此适合于大学为基础的研究和开发。这项研究的结果和开发的方法将被整合到研究生和本科生课程。预计K-12学生和高中教师将参与研究，这将提供工程曝光并激发工程兴趣。

The objective of this research is to develop a signaling scheme that produces near zero simultaneous switching noise for I/O circuits switching in a package or printed circuit board. In present packages and printed circuit boards, this is caused by the cavity resonances produced between the power and ground planes due to return path discontinuities. The approach is to replace the power planes using transmission lines that are matched at the source, thereby leading to un-interrupted current return paths. This approach can be applied to both 2D and 3D integrated systems.Intellectual Merit: Today's electronic systems use a low impedance power distribution network. Contrary to this practice, high impedance transmission lines can be used to supply power, thereby eliminating the need for hundreds of capacitors. Using the proposed interconnection topology, it is expected that copper wires in the package would be sufficient to achieve a bandwidth of 1.6TBps or better between multi-core processors and memory.Broader Impacts: The high-risk, far-reaching approach investigated in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research and development. The findings from this research and the approaches developed will be integrated into graduate and undergraduate courses. K-12 students and high school teachers are expected to participate in research, which provides engineering exposure and stimulates engineering interest.