US-Ireland R&D Partnership: Si-compatible, Strain Engineered Staggered Gap Ge(Sn)/InxGa1-xAs Nanoscale Tunnel Field Effect Transistors

在过去的五十年里，基于硅（Si）的晶体管技术的积极缩小导致了计算能力的指数级增长，这是由于相应的逻辑器件密度和操作速度的扩大。此外，这种持续的小型化导致了廉价、强大和紧凑的计算设备的扩散，使硅微电子成为现代社会必不可少的和无处不在的方面。为了延长这些趋势，并解决晶体管技术接近原子长度尺度时出现的基本技术挑战，对新型晶体管材料和器件架构的研究至关重要。采用新的半导体材料，如锗（Ge）、锗锡（GeSn）和砷化铟镓（InGaAs），以及晶体管架构，如基于量子力学隧道原理的隧道场效应晶体管，为未来集成电路降低功耗和提高每瓦性能提供了途径。然而，与硅不同的是，这些新型晶体管技术和材料并没有从半个世纪的工艺成熟中受益。因此，本研究的中心重点是研究新型Ge(Sn)/InGaAs隧道晶体管在大面积、低成本Si衬底上的材料和光学特性、电学特性和非均质集成。此外，在硅上实现非硅材料和器件的单片异质集成方案是一个变革性的目标，它利用了现有的成熟的硅工艺基础设施，并具有新颖的、可扩展的非硅晶体管技术的性能优势。通过解决这些技术挑战，这项研究将有利于广泛的应用，包括工业、医疗、商业和个人使用，这些应用需要具有成本竞争力、低功耗和高性能的计算设备。此外，合作伙伴之间的国际合作互动允许一个全面的项目，通过交换项目培训和指导学生，接触爱尔兰的教育和文化，并为持续和不断增长的美爱合作奠定基础。为了证明所提出方法的可行性，必须解决几个关键的技术和科学问题，包括：(i) Ge(Sn)/InGaAs异质结构的材料合成和表征；（ii）提出的互补Ge(Sn)/InGaAs隧道晶体管器件架构的数值模拟；（iii）开发制造n沟道和p沟道Ge(Sn)/InGaAs隧道晶体管的工艺流程；（四）实施Si集成方案。为了解决(i), （iii）和（iv），拟议的研究将利用最先进的内部外延生长（相互连接的iv族和iii - v族分子束外延室），协作材料表征和模拟（例如，高分辨率x射线衍射，透射电子显微镜，光致发光光谱，ab-initio界面分子动力学和电子带结构模拟），以及内部纳米电子制造设施。为了解决（ii），将利用商业和定制软件包的组合来开发精确的、实验校准的Ge(Sn)/InGaAs器件模型，这些模型是大规模电路集成可行性所必需的。通过研究这些主题，本研究将阐明许多尚未探索的基础研究途径，包括：(a)控制IV族（Ge, GeSn）和III-V族（In, Ga, As）之间的异质界面原子混合和原子突变隧道结的形成；(b) iii族或v族表面端接对电子、光学和能带对准特性的作用；(c) Ge(Sn)/InGaAs tfet中有效隧穿势垒高度的降低，以及通过外延拉伸应变工程和Sn合金掺入将Ge（Sn）转化为直接带隙材料；(d) iv族和III-V族材料的同时化学和电钝化；(e)通过最小化Si上的原位III-V缓冲结构中的螺纹位错和反相域来实现器件质量的Si外延异质结构。通过对上述问题的全面研究和理解，本研究将为实现下一代非硅纳米电子学提供一条途径，通过将技术和计算创新扩展到物理缩放极限，将有利于工业和社会。

The aggressive down-scaling of silicon (Si)-based transistor technology over the past five decades has resulted in an exponential increase in computing power due to the corresponding up-scaling of logic device densities and operational speeds. Moreover, this continued miniaturization has led to the proliferation of affordable, powerful, and compact computing devices that have made Si microelectronics an essential and ubiquitous aspect of modern society. To prolong these trends and address the fundamental technical challenges that have arisen as transistor technology approaches the atomic length scale, research into novel transistor materials and device architectures is paramount. The adoption of new semiconducting materials, e.g., germanium (Ge), germanium-tin (GeSn) and indium gallium arsenide (InGaAs), and transistor architectures, e.g. tunnel field-effect transistors operating on the principle of quantum mechanical tunneling, offer paths to reduce power consumption and increase performance-per-watt in future integrated circuits. However, unlike Si, these novel transistor technologies and materials do not benefit from half-a-century of process maturity. Therefore, the central thrusts of this research are to investigate the materials and optical properties, electrical characteristics, and heterogeneous integration of novel Ge(Sn)/InGaAs tunnel transistors on large area, cost-effective Si substrates. Moreover, the implementation of a monolithic, heterogeneous integration scheme for non-Si materials and devices on Si is a transformative goal that leverages the existing mature process infrastructure for Si with the performance benefits of novel, scalable non-Si transistor technologies. By addressing these technical challenges, this research will benefit a wide range of applications, ranging from industrial, medical, commercial and personal use that require cost-competitive, low-power and high-performance computational devices. Furthermore, this international co-operative interaction between partners allows for a comprehensive project that trains and mentors students through exchange programs, exposure to education and culture in Ireland as well as lay a foundation for continued and growing US-Ireland collaboration. To demonstrate the viability of the proposed approach, several key technical and scientific concerns must be addressed, including: (i) materials synthesis and characterization of Ge(Sn)/InGaAs heterostructures; (ii) numerical simulation of the proposed complimentary Ge(Sn)/InGaAs tunnel transistor device architectures; (iii) development of a process flow for fabricating the n- and p-channel Ge(Sn)/InGaAs tunnel transistors; and (iv) implementation of an integration scheme on Si. To address (i), (iii), and (iv), the proposed research will utilize the state-of-the-art in-house epitaxial growth (interconnected group-IV and III-V molecular beam epitaxy chambers), collaborative materials characterization and simulation (e.g., high-resolution x-ray diffraction, transmission electron microscopy, photoluminescence spectroscopy, and ab-initio interfacial molecular dynamics and electronic band structure simulation), and in-house nanoelectronics fabrication facilities. To address (ii), a combination of commercial and custom software packages will be leveraged to develop precise, experimentally-calibrated Ge(Sn)/InGaAs device models necessary for large-scale circuit integration feasibility. By investigating these topics, this research will elucidate numerous as-of-yet unexplored avenues of fundamental research, including: (a) the control of heterointerface atomic intermixing between group IV (Ge, GeSn) and III-V (In, Ga, As) species and formation of atomically abrupt tunnel junctions; (b) the role of group-III or group-V surface termination on the electronic, optical and energy band alignment properties; (c) the reduction of effective tunneling barrier heights in Ge(Sn)/InGaAs TFETs and conversion of Ge(Sn) to a direct band-gap material through epitaxial tensile strain engineering and Sn alloy incorporation; (d) the simultaneous chemical and electrical passivation of group-IV and III-V materials; and (e) the realization of device-quality epitaxial heterostructures on Si through minimization of threading dislocations and anti-phase domains in in-situ III-V buffer architectures on Si. Through a comprehensive examination and understanding of the aforementioned issues, this research will offer a path to achieve next-generation, non-Si nanoelectronics that will benefit industry and society via extending technological and computational innovation towards the physical scaling limit.