SaTC: STARSS: Small: Design of Low-Power True Random Number Generator based on Adaptive Post-Processing

SaTC：STARSS：小型：基于自适应后处理的低功耗真随机数生成器设计

• 批准号: 1714496
• 负责人: Visvesh Sathe
• 金额: $ 24.67万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-10-01 至 2020-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1714496&HistoricalAwards=false
• 关键词: SaTC; STARSS; Small; Design; Low

Nearly all security protocols rely on random numbers. A hardware True Random Number Generator (TRNG) is a circuit implemented within an Integrated Circuit (IC). If a TRNG is not truly random, an adversary may be able to break into the security of a protocol. Hence true randomness is an important property. TRNG circuits are often large and power hungry. There is a need for low-power TRNG in battery operated devices or in energy constrained environments. This proposal addresses that need. The proposed research explores an alternative to traditional TRNG designs. Instead of taking on considerable design complexity and energy dissipation by directly turning circuits to generate high quality random numbers, it starts with a sufficiently good physical circuit random number generator, and then combines it with a robust low-power statistical post-processing unit to address both bias, and correlation between TRNG outputs. This results in a design where the first component is only required to provide some randomness, while the second component refines this randomness through decorrelation and bias removal to extract provably perfectly random sequence of bits akin to identical and independent fair coin flips. This design will be implemented in a silicon prototype. The proposed research is interdisciplinary involving applied probability, network security, and VLSI design.

几乎所有安全协议都依赖于随机数。硬件真随机数生成器 (TRNG) 是在集成电路 (IC) 内实现的电路。 如果 TRNG 不是真正随机的，对手可能能够破坏协议的安全性。因此，真正的随机性是一个重要的属性。 TRNG 电路通常很大且耗电。电池供电设备或能源受限环境中需要低功耗 TRNG。本提案满足了这一需求。 拟议的研究探索了传统 TRNG 设计的替代方案。它不是通过直接转动电路来生成高质量随机数来承担相当大的设计复杂性和能耗，而是从足够好的物理电路随机数生成器开始，然后将其与强大的低功耗统计后处理单元相结合，以解决 TRNG 输出之间的偏差和相关性。这导致设计中，第一个组件只需要提供一些随机性，而第二个组件通过去相关和偏差消除来细化这种随机性，以提取类似于相同且独立的公平硬币翻转的可证明完全随机的位序列。该设计将在硅原型中实现。拟议的研究是跨学科的，涉及应用概率、网络安全和超大规模集成电路设计。

项目成果

A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction

具有集成去相关和偏差校正功能的 65 nm CMOS 3.2 至 86 Mb/s 2.58 pJ/bit 高度数字化真随机数发生器

• DOI: 10.1109/lssc.2019.2896777
• 发表时间: 2018
• 期刊: IEEE Solid-State Circuits Letters
• 影响因子: 2.7
• 作者: Pamula, Venkata Rajesh;Sun, Xun;Kim, Sung Min;Rahman, Fahim ur;Zhang, Baosen;Sathe, Visvesh S.
• 通讯作者: Sathe, Visvesh S.