FoMR: IPC-MASTA: Boosting IPC with Microarchitectural Support for Tightly-Coupled Accelerators

FoMR：IPC-MASTA：通过紧耦合加速器的微架构支持增强 IPC

• 批准号: 2010830
• 负责人: Mikko Lipasti
• 金额: $ 26.99万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-07-01 至 2024-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2010830&HistoricalAwards=false
• 关键词: FoMR; IPC; MASTA; Boosting; Microarchitectural

Over fifty years of advances in high-performance microprocessors have enabled countless benefits to society, including unprecedented advances in many scientific disciplines and healthcare delivery, improvements in economic efficiency and productivity, new forms of entertainment, and the creation of entirely new industries and business models. However, both the computing industry and semiconductor technology are at a cross-roads, and new approaches are needed to sustain the historical trend of performance increases and overcome the barriers faced by conventional approaches to improving processor performance. A promising approach employed in recent designs has been to integrate function-specific hardware accelerators next to the processor, enabling efficient and high-performance offloading of common, coarse-grained, compute-intensive operations—such as decoding of video data—from the general-purpose CPU. This project will explore an emerging variant of this approach, where the accelerators are designed to perform frequent, fine-grained operations, are coupled tightly to the processor core, and are expected to be more flexible, broadly applicable, and easier to integrate into the software development model familiar to the vast majority of today’s programmers. This research is expected to lead to several practical artifacts along with scientific and conceptual advances that will enable designers of future microprocessors to more easily integrate such accelerators, as well as preparation and training of graduate students with potential for direct technology transfer through their future employment.This project seeks to conduct a detailed study of tightly-coupled accelerators (TCAs), uncovering the trade-offs and complexities of integrating them into modern processors. To date, little has been done to characterize and optimize the many design considerations that can have critical impact on overall processor performance and power consumption. The project will approach this problem in three phases. The initial phase will develop an analytical model for assessing the impact of integrating TCAs in high-performance CPUs. Next, a comprehensive study of the microarchitectural implications of TCAs will uncover key design challenges, opportunities, and novel solutions for integrating TCAs. The final phase will investigate reconfigurable TCAs, which are intended to achieve the seemingly contradictory goals of specialized acceleration as well as broad applicability. The project will investigate several avenues for general-purpose acceleration using our reconfigurable TCA architecture, showing that it is possible to reap the best of both worlds of specialization and generalization without dedicating significant hardware real estate nor design effort.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

50多年来，高性能微处理器的进步为社会带来了无数好处，包括许多科学学科和医疗保健服务的前所未有的进步，经济效率和生产力的提高，新的娱乐形式以及全新行业和商业模式的创造。然而，计算行业和半导体技术都处于十字路口，需要新的方法来维持性能提高的历史趋势，并克服传统方法所面临的障碍来提高处理器性能。在最近的设计中采用的一种很有前途的方法是在处理器旁边集成特定功能的硬件加速器，从而实现从通用CPU高效和高性能地卸载常见的粗粒度计算密集型操作，例如视频数据的解码。该项目将探索这种方法的一种新兴变体，其中加速器旨在执行频繁的细粒度操作，与处理器核心紧密耦合，并且预计将更加灵活，适用范围更广，更容易集成到当今绝大多数程序员熟悉的软件开发模型中。这项研究预计将导致几个实际的工件沿着科学和概念的进步，这将使未来的微处理器的设计者能够更容易地集成这种加速器，以及准备和培训研究生，通过他们未来的就业直接技术转让的潜力。揭示了将它们集成到现代处理器中的权衡和复杂性。到目前为止，很少有人做的特点和优化的许多设计考虑因素，可能会对整体处理器的性能和功耗的关键影响。该项目将分三个阶段处理这一问题。初始阶段将开发一个分析模型，用于评估在高性能CPU中集成TCA的影响。接下来，对TCA的微架构含义的全面研究将揭示关键的设计挑战、机遇和集成TCA的新解决方案。最后一个阶段将研究可重构的TCA，其目的是实现专业化加速和广泛适用性这两个看似矛盾的目标。该项目将调查使用我们的可重配置的TCA架构进行通用加速的几种途径，表明有可能在不投入大量硬件真实的资产或设计工作的情况下，获得专业化和通用化两个世界的最佳效果。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Modeling Architectural Support for Tightly-Coupled Accelerators

紧耦合加速器的建模架构支持

• DOI: 10.1109/ispass48437.2020.00045
• 发表时间: 2020
• 期刊: ISPASS Proceedings
• 作者: Schlais, David J.;Zhuo, Heng;Lipasti, Mikko H.
• 通讯作者: Lipasti, Mikko H.

Value Locality Based Approximation With ODIN

使用 ODIN 进行基于值局部性的近似

• DOI: 10.1109/lca.2020.3002542
• 发表时间: 2020
• 期刊: IEEE Computer Architecture Letters
• 影响因子: 2.3
• 作者: Singh, Rahul;Ravi, Gokul Subramanian;Lipasti, Mikko;Miguel, Joshua San
• 通讯作者: Miguel, Joshua San

Work-in-Progress: NoRF: A Case Against Register File Operands in Tightly-Coupled Accelerators

• DOI: 10.1109/cases55004.2022.00028
• 发表时间: 2022-10
• 期刊: 2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
• 作者: David J. Schlais;Heng Zhuo;Mikko H. Lipasti

Systems-on-Chip with Strong Ordering

具有强排序功能的片上系统

• DOI: 10.1145/3428153
• 发表时间: 2021
• 期刊: ACM Transactions on Architecture and Code Optimization
• 影响因子: 1.6
• 作者: Puthoor, Sooraj;Lipasti, Mikko H.
• 通讯作者: Lipasti, Mikko H.

BlurNet: Defense by Filtering the Feature Maps

• DOI: 10.1109/dsn-w50199.2020.00016
• 发表时间: 2019-08
• 期刊: 2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)
• 作者: Ravi Raju;Mikko H. Lipasti