Collaborative Research: Defect Immune, Topologically Protected Devices for Ultra-Low Power Electronics

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Imperfections in materials, such as defects or edge roughness, often severely limit electronic device performance. This is especially problematic at the nanoscale where even a single atomic defect can drastically disrupt transport. Devices that are tolerant to these imperfections are thus the key to future technologies. The investigation of the fundamental properties and integration of two new defect-tolerant device concepts is proposed, enabled by novel 2D and 3D topological insulators (TIs), that exhibit unprecedented low-power, room temperature performance and functionalities only achievable using these unique materials. This tolerance to defects will enable nanoelectronics beyond the currently known limits and will specifically impact the national grand challenge of enabling ultra-low-power, post-silicon electronics and represent significant progress in an area of national technological strength, semiconductor electronics. A team of researchers with complementary expertise, including junior investigators complemented by accomplished senior professors, will address the challenges of the proposed work. This research will also broaden scientific and educational participation by creating a pipeline of pre-college and undergraduate students motivated to study science and engineering at universities through, for example, NSF-sponsored Research Experiences for Undergraduates (REU) programs and collaborations with national laboratories and industry partners. The researchers will also engage the public through science cafe programs where faculty members present their research in local pubs and restaurants.This collaborative research team will elucidate the fundamental science and technological implications of new topological insulator (TI)-based nanoelectronic device concepts that can operate at low-power, well above room temperature. Two complementary research threads will be pursued, both of which will enable a new, ultra-low-power, topologically protected device made of bismuth-based materials: 1) a 2D TI-based field-effect transistor that is immune to materials and device imperfections such as defects and line-edge roughness, and 2) a 3D TI-based tunneling device utilizing spin-filtering to exhibit negative differential resistance with unprecedented peak-to-valley ratio performance. TI growth by molecular beam epitaxy (Hinkle) will focus on 2D Bi and 3D Bi2Se3, which have predicted room-temperature device applications. Surface and edge state detection and chemical/structural properties will be investigated using in-situ techniques (Wallace). Theoretical studies including density functional theory (DFT), scattering, and mobility calculations (Vandenberghe) will be employed. Advanced 2- and 3-terminal devices will be fabricated (Banerjee) and these device characteristics will be evaluated in NAND gates. This research will provide materials and device concepts for advanced low-power, high-performance logic, memory, and even oscillatory neuromorphic applications using TIs, a class of devices which are extremely robust against defects/impurities. A TI and 2D materials property and benchmarking database through collaboration with NIST will also be established.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.