Memristive tunnel junctions and CMOS integration

忆阻隧道结和 CMOS 集成

• 批准号: 261986629
• 负责人: Professor Dr. Hermann Kohlstedt
• 金额: --
• 依托单位: Arbeitsgruppe Nanoelektronik
• 依托单位国家: 德国
• 项目类别: Research Units
• 财政年份: 2014
• 资助国家: 德国
• 起止时间: 2013-12-31 至 2020-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/261986629?language=en
• 关键词: Memristive; tunnel; junctions; CMOS; integration

In the last couple of years promising computing concepts based-on memristive devices have been presented. Nevertheless, their hardware realization is limited by a lack of reliable devices and a thorough understanding of the involved switching mechanisms on a microscopic scale. The main goal of this subproject is to close the gap between promising computing concepts and the hardware realization. CMOS-compatible devices for neuromorphic circuits will be developed. In the focus of our investigation are interface-based memristive devices. The resistance switching mechanism results from changes at a Schottky-like contact in conjunction with a varying electron tunnelling probability. This so called double barrier memristive device, has been developed in the first founding period of this project. In the current funding period the underlying chemical and physical effect, which leads to the analogue interface-based resistance switching of those devices, will be further explored and transferred to CMOS compatible materials (in particular HfOx as memristive layer). In particular, it is intend to transfer double barrier memristive devices into the BiCMOS pilot line of the IHP. At the device level, the yield, variability, predictability, energy efficiency, and the material and process compatibility to the Silicon technology will be studied. Further we will to set-up small test circuits, which allows to investigate the behaviour of the realized devices within a network environment. Those circuits should furthermore facilitate the development of integrated circuits within the C subprojects of the research unit.

在过去的几年里，基于忆阻器件的有前途的计算概念已经提出。然而，它们的硬件实现受到缺乏可靠设备和对微观尺度上所涉及的切换机制的透彻理解的限制。这个子项目的主要目标是缩小有前途的计算概念和硬件实现之间的差距。将开发用于神经形态电路的CMOS兼容器件。我们研究的重点是基于界面的忆阻器件。电阻切换机制的结果从一个肖特基接触结合不同的电子隧穿概率的变化。这种所谓的双势垒忆阻器件，已经在该项目的第一个创始期开发。在目前的资助期内，将进一步探索导致这些器件基于模拟界面的电阻切换的潜在化学和物理效应，并将其转移到CMOS兼容材料（特别是HfOx作为忆阻层）。特别是，它旨在将双势垒忆阻器件转移到IHP的BiCMOS试验线中。在器件层面，将研究产量、可变性、可预测性、能效以及与硅技术的材料和工艺兼容性。此外，我们将设置小的测试电路，这允许调查网络环境中实现的设备的行为。这些电路应进一步促进研究单位C分项目内集成电路的开发。