Fabrication of High-Speed Amorphous-Silicon Integrated Circuits

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Amorphous-Silicon Thin-Film Transistors (a-Si FETs) are studying extensively, but there is a intrinsic difficulty in a-Si FETs caused by low field-effect mobility of a-Si. The object of this study is to improve FET performances by developing a novel FET fabrication process and a FET structure, and also to improve a-Si circuit performances by developing a novel circuit configuration.First, we have developed a novel thermal-oxidation method of silicon at temperatures of as low as 250゜C. Electrical properties of the oxide and its interface have been evaluated. The breakdown field strength was more than 4MV/cm, the resistivity more than <10^(14)> <omega> and the interface state density about <10^(11)> / <cm^2> eV. By using this method we have developed a nearly ideal a-Si MOS FET and showed that the FET has the mobility of as high as 2.9 <cm^2> /Vs, the on-off current ratio of more than <10^6> and half-decay time in the current of as long as <10^(10)> years.Second, we have invented a novel short channel a-Si FET structure where conventional restrictions caused by photo-lithography have been completely eliminated. Two-dimensional device simulation program has been developed and has been used to accumulate device design data. The self-aligned short-channel FET has been fabricated by using reactive ion etching method, and FET characteristics have been evaluated.Third, a novel high speed logic circuit has been proposed which is formed by a-Si FETs and a-Si Schottky barrier diodes. Computer simulation indicated that the novel circuit with 1 <micro> m FET can be operated at multi-MHz rates. A prototype device has been fabricated and its performance at 80kHz has been evaluated.