Efficient Power Amplifiers for Aggressive Duty-Cycling(EPAAD)

未来毫米波通信的能耗必须降低。仅在短持续时间内需要峰值数据速率。受人工智能(AI)启发的自适应占空比提供持续时间低至子μS范围的数据包非常有吸引力，以节省能源。休眠时间可以是活动操作时间的10000倍。后者可以在类似范围内，甚至可以小于直流工作点切换(OPS)时间。因此，总能耗不仅由活动操作确定，还由休眠和OPS状态决定。在收发信机中，DC功率的主要部分由功率放大器(PA)吸收。针对主动运行过程中功率放大器能效降低的问题，国内外发表了大量的研究成果。直到今天，在睡眠和OPS状态下最大限度地减少PA的能量消耗上花费的注意力要少得多。为了为新一类超高效积极占空比铺平道路，EPAAD探索了将OPS和睡眠能量降至最低的方法。由于可以选择以最小的直流开销实现超短数据突发，因此可以节省能源。采用E类功率放大器，以使主动工作所需的能量尽可能低。OPS时间主要由与处理电源电流变化的馈电电感、控制节点、功率放大器铁心、LC阻抗匹配、RF接地分流和交流耦合电容器相关的时间常数决定。为了减小馈电电感和相关的时间常数，我们采用了逆E类结构。共源共栅结构的晶体管堆叠降低了功率放大器的密勒效应和RC常数。差动拓扑将RF并联电容器的尺寸和延迟降至最低。为了最大限度地减少休眠模式中的泄漏，必须拉低共源级的栅极电压，从而导致更长的OPS持续时间。在将下栅极保持在高电平的同时切换上栅极将导致较低的OPS时间。因此，我们研究了采用层叠晶体管顺序开关的新型控制方案，以同时降低OPS和休眠能量。为了验证这些方法，在22 nm FDSOI芯片上设计了一个28 GHz的功率放大器。GlobalFoundries为我们提供针对前沿品质因数的未释放晶体管，漏源击穿电压为≈4.2V，同时仍提供≈250 GHz的高最大振荡频率。关键的量化功放目标是记录开/关OPS时间&lt；10 ns、睡眠泄漏电流&lt；500 nA、射频输出功率&gt；24 dBm和40%功率附加效率(PAE)。对于这项研究，DFG资金是由德累斯顿理工大学的弗兰克·埃林格申请的。基于这些见解，来自哥伦比亚的Pontifia University Jiveriana(PUJ)的Méndez教授执行了关于全收发器基于模拟的能量和性能调查的其他任务。

The energy consumption of future millimetre-wave communications has to be reduced. Peak data rates are only required during a short duration. Artificial intelligence (AI) inspired adaptive duty-cycling providing data packages with duration down to the sub-μs range is very attractive to save energy. The sleep times can be > 10 000 times longer than the active operation times. The latter can be in a similar range or even smaller than the DC operation point switching (OPS) times. Thus, the overall energy consumption is not only determined by the active operation but also by the sleep and OPS states. In transceivers, a major part of the DC power is drawn by the power amplifiers (PAs). A huge number of works were published treating the reduction of the PA energy efficiency in active operation. Until today, much less attention was spent on the minimization of the PA energy consumed during the sleep and OPS states. To pave the way for a new class of ultra-efficient aggressive duty-cycling, EPAAD explores approaches to minimize the OPS and sleep energies. Due to the option to go for ultra-short data bursts at minimum DC overhead, energy can be saved. Class-E PAs are employed to keep also the energy for active operation as low as possible. The OPS times are mainly determined by the time constants associated with the feeding inductance handling the supply current change, control nodes, PA core, LC-impedance matching, RF-ground-shunt and AC-coupling capacitors. To reduce the feeding inductance and the associated time constant, we go for an inverse class-E architecture. Cascode-like transistor stacking reduces the Miller effect and the RC constant of the PA core. A differential topology minimizes the required sizes and delays of the RF-shunt capacitors. To minimize the leakage in sleep mode, the gate voltage of the common source stage has to be pulled down leading to a larger OPS duration. The switching of the upper gates while keeping the lower gate at high level results in lower OPS times. Hence, we investigate novel control schemes with sequential switching of stacked transistors to reduce both the OPS and sleep energies. To verify the approaches, a 28 GHz PA is designed in 22 nm FDSOI CMOS. Globalfoundries offers us non-released transistors targeting a leading-edge figure of merit with drain source breakdown voltage of ≈ 4.2 V while still providing a high maximum frequency of oscillation of ≈ 250 GHz. Key quantitative PA goals are record on/off OPS times < 10 ns, sleep leakage currents < 500 nA, an RF output power > 24 dBm and 40 % power added efficiency (PAE). For this research, DFG funding is requested by Frank Ellinger at TU Dresden. Based on these insights, additional tasks regarding simulation-based energy and performance investigations of full transceivers are performed by Prof. Méndez from Pontificia Universidad Javeriana (PUJ) in Columbia.