Mixed-Signal Electronics and Digital Signal Processing for Energy-Efficient Wireless Communication above 100Gbps (MEDSEEC-100)

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Enabling terabit wireless communication systems implies the use of very large channel bandwidths of 25-50 GHz, which are available in the subterahertz frequency range beyond 100 GHz. A major challenge for wireless communication with data rates in the order of 100 Gbit/s is the receiver design. In particular, at the necessarily high sampling rates, the analog-to-digital converters (ADCs) become a major energy consumption bottleneck.In contrast to classical multi-bit quantization, 1-bit quantization with significant oversampling can be an alternative energy-efficient approach. The achievable power savings result from more relaxed linearity requirements on the receiver, limited need of automatic gain control, and the application of simpler ADC architectures. Moreover, 1-bit quantization with oversampling is a perfect match for nm-scale semiconductor processes that have a decreased voltage range but allow for a high time resolution (e.g., the GlobalFoundries process 22FDX operates at 0.4-0.8 V with a maximum frequency of oscillation fmax ≈ 370 GHz).In our previous work we have already studied several components of such terabit wireless communication systems based on oversampled 1-bit quantization. We developed an adapted modulation and signaling scheme, radio frontend components providing sufficient bandwidth for carrier frequencies around 200GHz, and circuits for temporally oversampled 1-bit quantization. Moreover, we derived fundamental limits on channel parameter estimation and first estimation algorithms. Based on these results, we want to study key design aspects of the realization of energy-efficient mixed signal electronics and digital signal processing for receivers using 1-bit quantization. The aim is to understand the trade-offs between energy efficiency of the analog hardware and the communication performance. Since a key aspect of a receiver is channel parameter estimation, we want to find parameter estimation objective functions that are suitable for receivers that use 1-bit quantization, from which we then systematically derive practical timing estimators. Moreover, we will study the impact of distortions by the analog frontend and sampling jitter on the communication performance. To achieve high energy efficiency in case of varying rate requirements, we further study circuits for 1-bit ADC of minimum power consumption with two concurrent approaches. First, improving our previous results at sampling rates of 200Gbit/s, the core blocks of the ADCs will introduce novel adaptivity and enable precise control of the sampling rate, optimizing power consumption and realizing automatic compensation of process and temperature variation. Second, the circuits will be designed to be switched very rapidly, enabling further reductions in power consumption when only short bursts of data need to be transmitted at peak rate. To further improve the efficiency of the hardware, we will realize the circuits in an advanced 22 nm FD-SOI CMOS technology.