Neural LSI's Possessing Autonomous Defect Self-repairing Capability
神经LSI具备自主缺陷自我修复能力
基本信息
- 批准号:10450131
- 负责人:
- 金额:$ 2.88万
- 依托单位:
- 依托单位国家:日本
- 项目类别:Grant-in-Aid for Scientific Research (B).
- 财政年份:1998
- 资助国家:日本
- 起止时间:1998 至 2000
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
We have chosen the self-organizing map (SOM) as the target network in the neural networks, and evaluated its autonomous fault repairing capability quantitatively. Especially, in the project, we have proposed a defect model in which the defective neurons output arbitrary stuck values. From the analysis of the model, the following facts are shown (proved).1) The SOM can repair the defective neurons autonomously, if the defective neurons'outputs are larger than the critical stuck output, which is derived from the proposed defect model.2) The new criteria "critical stuck output" can be used widely even in the real applications such as image compression and face image recognition.Furthermore, in the project, we have also evaluated fault tolerance of the evolutionary algorithm (genetic algorithms, genetic program etc.) because the high fault tolerance can be also expected not only in the neural networks but also other algorithms based on the biological information processing. In order to evaluate the fault tolerance, we have carried out fault injection experiments using simulation programs and the prototype machine constructed based on reconfigurable LSI (FPGA). From the experimental results, it has been shown that the hardware based on the evolutionary algorithms also has high fault tolerance and graceful degradation against defective circuitsFrom wll those experimental results we have show that neural network LSIs and evolutionary algorithms-based LSIs has high fault tolerance and they can repair the defective circuits autonomously.
我们在神经网络中选择自组织映射(SOM)作为目标网络,并定量评价了其自主故障修复能力。特别是在项目中,我们提出了一个缺陷模型,其中有缺陷的神经元输出任意的卡值。通过对模型的分析,证明了以下事实。1)当缺陷神经元的输出大于缺陷模型导出的临界粘滞输出时,SOM可以自主修复缺陷神经元。2)即使在图像压缩和人脸图像识别等实际应用中,“临界卡滞输出”新标准也可以得到广泛应用。此外,在项目中,我们还评估了进化算法(遗传算法,遗传程序等)的容错性,因为不仅在神经网络中,而且在其他基于生物信息处理的算法中也可以期望具有高容错性。为了评估其容错性,我们利用仿真程序和基于可重构LSI (FPGA)构建的样机进行了故障注入实验。实验结果表明,基于进化算法的硬件对缺陷电路具有较高的容错能力和良好的降级能力。实验结果表明,神经网络lsi和基于进化算法的lsi具有较高的容错能力,能够自主修复缺陷电路。
项目成果
期刊论文数量(70)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
安永守利: "進化アルゴリズムによる超高速・耐故障パターン認識チップの開発"計測自動制御学会創発システムシンポジウム予稿集. 1-6 (1999)
Moritoshi Yasunaga:“使用进化算法开发超高速和容错模式识别芯片”仪器与控制工程师学会紧急系统研讨会论文集 1-6 (1999)。
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Moritoshi Yasunaga, Taro Nakamura, and Ikuo Yoshihara: "Sonar Spectrum Recognition Chip Designed by Evolutionary Algorithm"Proc. The IEEE and INNS Intl. Joint Conf. on Neural Networks, CD-ROM July. (1999)
Moritoshi Yasunaga、Taro Nakamura 和 Ikuo Yoshihara:“采用进化算法设计的声纳频谱识别芯片”Proc.
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- 影响因子:0
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安永守利,高橋雅聡,吉原郁夫: "進化的手法に基づく再構成可能な推論ハードウェア"情報処理学会論文誌. Vol.40,No.7. 3031-3042 (1999)
Moritoshi Yasunaga、Masatoshi Takahashi、Ikuo Yoshihara:“基于进化方法的可重构推理硬件”,日本信息处理学会汇刊,第 40 卷,第 3031-3042 期(1999 年)。
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- 影响因子:0
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M.Yasunaga,T.Nakamura,and I.Yoshihara: "Sonar Spectrum Recognition Chip Designed by Evolutionary Algorithm"Proc. The IEEE and INNS Intl. Joint Conf. on Neural Networks. (CD-ROM). (2000)
M.Yasunaga,T.Nakamura,I.Yoshihara:“进化算法设计的声纳频谱识别芯片”Proc。
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- 影响因子:0
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T.Tsuzuku, K.Takashima, and M.Yasunaga: "Study on the Fault Tolerance of Evolvable Hardware"Proc.IEICE Sougou-Taikai. D-10-23. 170 (2001)
T.Tsuzuku、K.Takashima 和 M.Yasunaga:“可进化硬件的容错性研究”Proc.IEICE Sougou-Taikai。
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YASUNAGA Moritoshi其他文献
YASUNAGA Moritoshi的其他文献
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Grant-in-Aid for Scientific Research (B)
Application of the Genetic Algorithms for ElectromagneticNoise Reduction Traces
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23650116 - 财政年份:2011
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Grant-in-Aid for Challenging Exploratory Research
Transmission Line Technology for Digital LSIs at 30GHz and Its Feasibility Study on Prototyping
30GHz数字LSI传输线技术及其原型可行性研究
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21360178 - 财政年份:2009
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13450163 - 财政年份:2001
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Autonomous Repairing Ability in Computers
计算机的自主修复能力
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08455185 - 财政年份:1996
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$ 2.88万 - 项目类别:
Grant-in-Aid for Scientific Research (B)
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