A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI

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In this research, we studied new layout design methods for layout design automation of deep-submicron VLSI chips so as to solve the problems considering the performance of circuits, hard/soft macros, and minimizing of design time.(1) Performance-driven circuit partitioning methodAn circuit partitioning algorithm under path delay constraints was proposed to optimize performance of circuit.(2) Performance-driven floorplanning methodsFor floorplanning design with hard/soft macros, we proposed a performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion and showed effectiveness of the method.(3) Performance-driven placement methodA timing-driven standard cell placement method based on cell-clustering and the new placement model, that is, ameba model was proposed.(4) Performance-driven routing methodsFor multi-routing layer model, we proposed a timing-driven hierarchical global routing method using a Steiner tree generation algorithm with wire sizing and buffer insertion.(5) Performance-driven hierarchical buffer-block planning methodWe proposed a hierarchical buffer block planning method, which divides the chip area into global bins, taking timing constraint into account.(6) Applications of an adaptive genetic algorithm to performance-driven layout designWe newly proposed an adaptive genetic algorithm based on elite degree and applied to the layout design problems. We also implemented the proposed GA as GA accelerator LSI chips to speed up the execution and got a prospect of high-speed execution of number 10 times for performance-driven layout methods.