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A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI

深亚微米高性能VLSI自动版图设计系统研究

基本信息

批准号：
12555097
负责人：
KOIDE Tetsushi
金额：
$ 7.55万
依托单位：
HIROSHIMA UNIVERSITY (2001)The University of Tokyo (2000)
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12555097/
关键词：
Deep-submicron VLSI ULSI CAD Layout design Floorplanning Placement and routing Genetic algorithm Performance-driven Buffer block planning シミュレーティドアニーリング ULSI

项目摘要

In this research, we studied new layout design methods for layout design automation of deep-submicron VLSI chips so as to solve the problems considering the performance of circuits, hard/soft macros, and minimizing of design time.(1) Performance-driven circuit partitioning methodAn circuit partitioning algorithm under path delay constraints was proposed to optimize performance of circuit.(2) Performance-driven floorplanning methodsFor floorplanning design with hard/soft macros, we proposed a performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion and showed effectiveness of the method.(3) Performance-driven placement methodA timing-driven standard cell placement method based on cell-clustering and the new placement model, that is, ameba model was proposed.(4) Performance-driven routing methodsFor multi-routing layer model, we proposed a timing-driven hierarchical global routing method using a Steiner tree generation algorithm with wire sizing and buffer insertion.(5) Performance-driven hierarchical buffer-block planning methodWe proposed a hierarchical buffer block planning method, which divides the chip area into global bins, taking timing constraint into account.(6) Applications of an adaptive genetic algorithm to performance-driven layout designWe newly proposed an adaptive genetic algorithm based on elite degree and applied to the layout design problems. We also implemented the proposed GA as GA accelerator LSI chips to speed up the execution and got a prospect of high-speed execution of number 10 times for performance-driven layout methods.

在本研究中，我们研究了新的版图设计方法的布局设计自动化的深亚微米超大规模集成电路芯片，以解决的问题，考虑性能的电路，硬/软宏，并尽量减少设计时间。(1)性能驱动的电路划分方法提出了一种基于路径时延约束的电路划分算法，以优化电路的性能。(2)性能驱动的布图规划方法对于硬/软宏的布图规划设计，我们提出了一种性能驱动的布图规划方法，该方法具有精确的面积和互连延迟估计，并通过布线尺寸和缓冲器插入来实现，并证明了该方法的有效性。(3)性能驱动的布局方法提出了一种基于单元聚类的时间驱动的标准单元布局方法，并提出了一种新的布局模型--阿米巴模型。(4)性能驱动的布线方法对于多布线层模型，我们提出了一种时间驱动的分层全局布线方法，使用Steiner树生成算法，结合布线尺寸和缓冲区插入。(5)性能驱动的分层缓冲区规划方法我们提出了一种分层缓冲区规划方法，该方法将芯片区域划分为全局区域，并考虑了时序约束。(6)自适应遗传算法在性能驱动版图设计中的应用我们新提出了一种基于精英度的自适应遗传算法，并将其应用于版图设计问题。我们也将所提出的遗传算法实现为遗传算法加速器大规模集成电路芯片，以加快执行速度，并得到了性能驱动的布局方法的高速执行数10倍的前景。