Developement of Contactless and Non-Destructive Capacitance-Voltage Measurement System in Ultra-High Vacuum

本研究的目的是研制用于超高真空（UHV）环境下半导体材料导电类型、杂质分布和表面态密度分布表征的“非接触非破坏性电容-电压（C-V）测量系统”，并研究各种类型的半导体表面，如重构表面、加工表面、覆盖有绝缘膜的表面、（1）该系统由以下四部分组成：（a）具有样品传输系统和泵系统的UHV室，（B）场板，其能够通过具有电容反馈的压电机构保持平行度和与样品表面的100- 300 nm的恒定距离，（c）基于光学方法的UHV间隙测量部分，所述光学方法利用由于倏逝波的穿透而引起的反射率的变化（古斯-汉欣效应），以及（d）包括C-V计的控制器。的基础压力 ...更多信息 腔室的压力在10 μ Torr的范围内<-10>。测量电容的分辨率为0.2fF，超高真空间隙距离为1 nm。(2)利用SiO_2/Si金属氧化物半导体（MOS）系统验证了该系统的有效性。所得非接触C-V曲线与理想C-V曲线吻合较好。(3)氢封端的Si表面显示出费米能级钉扎现象，这是由于位于价带上方0.6eV处的高密度离散表面态所致。(4)研究发现，在400 ℃以下的温度下，通过化学和热处理形成的氧化物覆盖的Si表面具有高密度的界面态，具有窄的U形连续分布，导致费米能级钉扎在杂化轨道电荷中性能级附近。（5）ECR N_2O等离子体处理的氮氧化硅表面无钉扎，界面态呈宽的U形连续分布，最小值为1.0 × 10 ~（-10）<11>eV·<-1>cm ~（-1）<-2>。Si_3N_4/SiO_2界面相分离结构的形成是实现无钉扎界面的主要原因。(6)非接触C-V测试结果直接表明，分子束外延GaAs（001）（2x 4）表面存在强烈的表面费米能级钉扎现象，这种钉扎现象不能用“扭结-受主模型”来解释。少

The purpose if this rsearch is to develop the "Contactless and Non-Destructive Capacitance-Voltage (C-V) Measurement System" for characterization of a conduction type, an impurity profile and a surface state density distribution of semiconductor materials in ultra-high vacuum (UHV) environment and to study various types of semiconductor surfaces such as reconstructed surfaces, processed surfaces, surfaces covered with ultrathin insulating films, etc. The main results obtained are listed below :(1) The system consists of four parts as follows : (a) An UHV chamber with a sample transfer system and a pump system, (b) a field plate which can maintain a parallelism and a constant distance of 100-300nm from a sample surface by piezo-mechanism with a capacitance feedback, (c) a UHV gap measurement part based on the optical method utilizing change in reflectivity due to penetration of evanescent wave (the Goos-Haenchen effect) and (d) a controller including C-V meter. The base pressure of the … More chamber was within the range of 10^<-10> Torr. The resolutions of a measured capacitance of 0.2fF and a UHV gap distance of 1nm were achieved, respectively.(2) The validity of the system was checked by using a SiO_2/Si metal oxide semiconductor (MOS) system. The obtained contactless C-V curve was well in agreement with the calculated ideal C-V curve.(3) The hydrogen-terminated Si surfaces showed the Fermi level pinning phenomena due to a high density of discrete surface state lying at 0.6eV above the valence band.(4) It was found that the Si surfaces covered with ultrathin oxides formed by chemical and thermal processes at temperatures below 400ﾟC had high-density interface states with narrow U-shaped continuous distributions, resulting in the Fermi level pinning near the hybrid orbital charge neutrality level.(5)The oxynitrided Si surface by ECR N_2O plasma was found to be pinning free, showing a wide, U-shaped, continuous interface state distribution with a minimum value of 1.0_x10^<11> eV^<-1>cm^<-2>. The formation of phase-separated Si_3N_4/SiO_2 interfacial structure was responsible for realization of the pinning free interface.(6) Contactless C-V results directly showed strong surface Fermi level pinning at the molecular-beam-epitaxy (MBE) grown GaAs (001) (2x4) surfaces, and the observed pinning behavior cannot be explained by the "kink-acceptor model". Less