Research and development of III-V quantum wire transistor-based logic and memory circuits operating near the quantum limit

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The purpose of this research was to study and develop novel logic and memory circuits that operate ultra-small delay-power product near the quantum limit by utilizing III-V compound semiconductor quantum wire transistors. The main results obtained are listed below :(1) A novel single electron memory device having a metal nano-dot for charging and a Schottky in-plane gate (IPG) quantum wire transistor (QWRTr) for dot-charge detection was proposed, fabricated and its basic operation was confirmed.(2) As single electron integrated circuits, single electron inverter circuits utilizing Schottky wrap gate (WPG) GaAs single electron transistor (SETs), including QWRTr road type inverters and complementary inverters, were designed, fabricated and characterized. Transfer gain larger than unity was obtained in the QWRTr road type inverter.(3) A novel approach for quantum logic circuits operating with ultra-low delay-power product near the quantum limit. It is based on implementation of a binary d … More ecision diagram (BDD) logic architecture by quantum wire transistors, was proposed. BDD node devices were fabricated using GaAs etched nanowire and nano-Schottkys and their basic operations were confirmed. Fundamental logic circuits constructed by integrating the BDD devices operated correctly.(4) Highly uniform and size-controllable InGaAs and GaAs embedded ridge quantum wire arrays were grown by selective MBE growth as basic starting structures for quantum wire transistors. Submicron-pitch high-density InGaAs quantum wire arrays were realized by an atomic hydrogen treatment and optimization of pre-growth process.(5) For successful surface passivation of III-V QWRTrs, their surfaces were characterized by scanning tunneling spectroscopy (STS). The mechanism of anomalous STS spectra was clarified. From this analysis, it was found that surface states with continuously distribution in space and energy cause surface Fermi level pinning. Surface passivation method using ultrathin Si interface control layer was optimized and verified by contactless C-V, PL and STS. Less