Research and development of III-V quantum wire transistor-based logic and memory circuits operating near the quantum limit

研究和开发在量子极限附近运行的基于 III-V 量子线晶体管的逻辑和存储电路

• 批准号: 12555083
• 负责人: HASEGAWA Hideki
• 金额: $ 8.58万
• 依托单位: HOKKAIDO UNIVERSITY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2001
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12555083/
• 关键词: quantum wire transistor; III-V compound semiconductor; quantum limit; logic circuit; memory; integrated circuit; Schottky gate; selective MBE growth

The purpose of this research was to study and develop novel logic and memory circuits that operate ultra-small delay-power product near the quantum limit by utilizing III-V compound semiconductor quantum wire transistors. The main results obtained are listed below :(1) A novel single electron memory device having a metal nano-dot for charging and a Schottky in-plane gate (IPG) quantum wire transistor (QWRTr) for dot-charge detection was proposed, fabricated and its basic operation was confirmed.(2) As single electron integrated circuits, single electron inverter circuits utilizing Schottky wrap gate (WPG) GaAs single electron transistor (SETs), including QWRTr road type inverters and complementary inverters, were designed, fabricated and characterized. Transfer gain larger than unity was obtained in the QWRTr road type inverter.(3) A novel approach for quantum logic circuits operating with ultra-low delay-power product near the quantum limit. It is based on implementation of a binary d … More ecision diagram (BDD) logic architecture by quantum wire transistors, was proposed. BDD node devices were fabricated using GaAs etched nanowire and nano-Schottkys and their basic operations were confirmed. Fundamental logic circuits constructed by integrating the BDD devices operated correctly.(4) Highly uniform and size-controllable InGaAs and GaAs embedded ridge quantum wire arrays were grown by selective MBE growth as basic starting structures for quantum wire transistors. Submicron-pitch high-density InGaAs quantum wire arrays were realized by an atomic hydrogen treatment and optimization of pre-growth process.(5) For successful surface passivation of III-V QWRTrs, their surfaces were characterized by scanning tunneling spectroscopy (STS). The mechanism of anomalous STS spectra was clarified. From this analysis, it was found that surface states with continuously distribution in space and energy cause surface Fermi level pinning. Surface passivation method using ultrathin Si interface control layer was optimized and verified by contactless C-V, PL and STS. Less

本研究的目的是利用III-V族化合物半导体量子线晶体管，研究和开发新型逻辑和存储电路，在量子极限附近操作超小的延迟功率积。（1）提出并制作了一种新型的单电子存储器件，该器件采用金属纳米点进行充电，采用肖特基面内栅（IPG）量子线晶体管（QWRTr）进行点电荷检测，并验证了其基本工作原理。(2)作为单电子集成电路，设计、制造和表征了采用肖特基绕栅（WPG）GaAs单电子晶体管（SET）的单电子反相器电路，包括QWRTr道路型反相器和互补反相器。在QWRTr道路型逆变器中获得大于1的传递增益。(3)量子极限附近超低延迟功率积量子逻辑电路的一种新方法。它基于二进制数据的实现， ...更多信息 提出了一种基于量子线晶体管的BDD逻辑结构。利用GaAs刻蚀纳米线和纳米肖特基器件制备了BDD节点器件，并确定了其基本工作原理。通过集成正确运行的BDD器件构建的基本逻辑电路。(4)采用选择性分子束外延技术生长了高度均匀且尺寸可控的InGaAs和GaAs嵌入脊形量子线阵列，作为量子线晶体管的基本起始结构。通过原子氢处理和优化预生长工艺，实现了亚微米间距的高密度InGaAs量子线阵列。(5)对于成功的III-V QWRTr的表面钝化，其表面的特征在于通过扫描隧道光谱（STS）。阐明了STS谱异常的机理。分析表明，表面费米能级钉扎是由空间和能量连续分布的表面态引起的。优化了采用硅界面控制层的表面钝化方法，并通过非接触C-V、PL和STS进行了验证。少

项目成果

H. Okada, H. Hasegawa: "Novel Single Electron Memory Device Using Metal Nano-Dots and Schottky In-Plane Gate Quantum Wire Transistors"Japanese Journal of Applied Physics. 40. 2797-2800 (2001)

H. Okada、H. Hasekawa：“使用金属纳米点和肖特基平面栅极量子线晶体管的新型单电子存储器件”日本应用物理学杂志。

C. Jiang, T. Muranaka, H. Hasegawa: "Structural and Optical Properties of 10 nm-Class InGaAs Ridge Quantum Wire Arrays with Sub-Micron Pitches Grown by Selective MBE on Patterned InP Substrate"Japanese Journal Applied Physics. (in press). (2002)

C. Jiang、T. Muranaka、H. Hasekawa：“通过选择性 MBE 在图案化 InP 衬底上生长的亚微米间距的 10 纳米级 InGaAs 脊量子线阵列的结构和光学特性”日本应用物理学杂志。

S. Anantathanasarn, H. Hasegawa: "Photoluminescence and Capacitance-Voltage Characterization of GaAs Surface Passivated by an Ultrathin GaN Interface Control Layer"Applies Surface Science. (in press). (2002)

S. Anantathanasarn、H. Hasekawa：“超薄 GaN 界面控制层钝化的 GaAs 表面的光致发光和电容电压特性”应用表面科学。

M.Yumoto: "Graph-Based Quantum Logic Circuits and Their Realization by Novel GaAs Multiple Quantum Wire Branch Switches Utilizing Schottky Wrap Gates"Microelectronics Engineering. (in press). (2002)

M.Yumoto：“基于图的量子逻辑电路及其利用肖特基包裹门的新型砷化镓多量子线分支开关的实现”微电子工程。

T.Hirano: "Electrochemical Formation of Self-Assembled InP Nanopore Arrays and Their Use as Templates for Molecular Beam Epitaxy Growth of lnGaAs Quantum Wires and Dots"Japanese Journal of Applied Physics. (in press). (2002)

T.Hirano：“自组装 InP 纳米孔阵列的电化学形成及其用作 lnGaAs 量子线和点分子束外延生长的模板”日本应用物理学杂志。