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Single Electron Integrated Circuits Based on A BDD Architecture Utilizing Quantum Dots Controlled by Nano-Schottky Gates

Single Electron Integrated Circuits Based on A BDD Architecture Utilizing Quantum Dots Controlled by Nano-Schottky Gates
基于采用纳米肖特基门控制的量子点的 BDD 架构的单电子集成电路
批准号:
13305020
负责人:
HASEGAWA Hideki
金额:
$35.44万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (A)
财政年份:
2001
资助国家:
日本
项目状态:
已结题
起止时间:
2001 至 2003

项目摘要

项目成果

HASEGAWA Hideki的其他基金

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中文摘要
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英文摘要
The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :(1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.(2)Elemental BDD devices (node devices) were realized using GaAs-based etched nanowires controlled by Schottky wrap gates (WPGs). They showed clear path switching characteristics from low temperature to room temperature. Power-delay product (PDP) of WPG-controlled single electron node devices was found to be as small as 10^<-22> J. Capability of GHz operation of WPG switches was confirmed experimentally by direct measurement of cut-off frequency.(3)B … More asic BDD logic circuits were fabricated on etched hexagonal nanowire networks controlled by WPGs and they operated correctly in a quantum regime at low temperature. They were found to be possible to operate correctly even at room temperature by trading off of PDP values. Then, high-density integrated circuit fabrication process realizing 45 million devices/cm^2 has been established. Utilizing this process, 2-bit BDD adder circuits were fabricated and their correct operations were confirmed, and 8-bit adder was also successfully fabricated.(4)Formation of hexagonal quantum nanowire network structures by MBE selective growth on patterned substrates was investigated and ultra-high density network fabrication technology of 240 million nodes/cm^2 for GaAs-based systems and 1 giga nodes/cm^2 for InP-based systems have been established. Branch switches and node devices were successfully fabricated utilizing the selectively MBE grown nanowires and their correct operations were confirmed.(5)For surface passivation of III-V semiconductor quantum nanostructures, a technique using ultra-thin Si and c-GaN interface control layers (ICLs) was investigated for III-V materials and optimized. It was found that GaAs surfaces was successfully passivated by preparation of Ga-rich (4×6) reconstructed surface as an initial surface for the ICL formation. Ultra-small minimum interface state density of 4×10^<10> cm^<-2>eV^<-1> was obtained in the SiO_2/GaAs interface. Less
期刊论文(261)
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会议论文
T.Sato: "Electrical Properties of Nanometer-Sized Schottky Contacts for Gate Control of III-V Single Electron Devices and Quantum Devices"Japanese Journal of Applied Physics. 40. 2021-2025 (2001)
T.Sato:“用于 III-V 单电子器件和量子器件栅极控制的纳米尺寸肖特基接触的电特性”日本应用物理学杂志。
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T.Yoshida: "Realization of UHV-Compativle Defect-Free Hydrogen Terminated Silicon Surfaces with the Use of UHV Contactless Capacitance-Voltage Method"Applied Surface Science. 175/176. 163-168 (2001)
T.Yoshida:“利用特高压非接触电容电压方法实现特高压兼容无缺陷氢封端硅表面”应用表面科学。
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T.Sato: "Current Transport and Capacitance-Voltage Characteristics of GaAs and InP Nanometer-Sized Schottky Contacts Formed by in situ Electrochemical Process"Applied Surface Science. 175/176. 181-186 (2001)
T.Sato:“通过原位电化学过程形成的 GaAs 和 InP 纳米尺寸肖特基接触的电流传输和电容电压特性”应用表面科学。
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H.Takahashi: "Process Characterization and Optimization for a Novel Oxide-Free Insulated Gate Structure for InP MISFETs Having Silicon Interface Control Layer"IEICE-C. E84-C10. 1344-1349 (2001)
H.Takahashi:“具有硅界面控制层的 InP MISFET 的新型无氧化物绝缘栅结构的工艺表征和优化”IEICE-C。
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223
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    • 批准号:
      21590521
    • 项目类别:
      Grant-in-Aid for Scientific Research (C)
    • 资助金额:
      $2.91万
    • 财政年份:
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    • 负责人:
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    • 依托单位:
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    • 批准号:
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    • 项目类别:
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    • 资助金额:
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    • 财政年份:
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    • 批准号:
      18360002
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $10.99万
    • 财政年份:
      2006
    • 负责人:
      HASEGAWA Hideki
    • 依托单位:
    Research and development of III-V quantum wire transistor-based logic and memory circuits operating near the quantum limit
    • 批准号:
      12555083
    • 项目类别:
      Grant-in-Aid for Scientific Research (B)
    • 资助金额:
      $8.58万
    • 财政年份:
      2000
    • 负责人:
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