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Research of Combination RF/Analog/Digital Global Integration technology

射频/模拟/数字组合全球集成技术研究

基本信息

批准号：
11305026
负责人：
TSUBOUCHI Kazuo
金额：
$ 25.69万
依托单位：
Tohoku University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1999
资助国家：
日本
起止时间：
1999 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-11305026/
关键词：
3D System on a chip RF Analog Digital All digital modem Vertical bus line Flip chip bonding Au-Au contact 電流モード回路LSI オールディジタルモデムマイクロバンプ実装 SS-CDMAネットワークグローバルインテグレーションデジタルアナログ混載システムトップダウン設計ハイブリッド集積化実装マイクロバンプワイヤレスマルチメ

项目摘要

In this research, we have investigated Si CMOS based mixed signal system LSI toward RF-CMOS system on a chip (SOC) for mobile terminal of next generation. Basic components such as FFT circuit with low power operation, SAW device, RF CMOS circuit, and low power digital LSI are studied. Especially, significant results about Si RF CMOS power amplifier, all digital 1-chip modem and packaging technology for 3D system chip have been obtained. We have proposed and confirmed the Si RF CMOS power amplifier operation using B-class push-pull construction with optimum design of n/p-MOSSFET. The power efficiency is more than 50 % and ACPR is less than -33dBc, which have been matched with W-CDMA. All digital 1-chip modem has been implemented with the area of 150x150 um^2. The divided digital clock has been used for RF carrier. The transmission performance with 1 dB degradation from theoretical value has been measured using Si LSI, which has been fabricated using 0.25 um Si process. We proposed the new concept of 3D package and vertical bus line with delay time limitation control method. Contact strength using flip-chip bonding as a basic flip-chip mounting technology has been evaluated. We have experimentally confirmed that Au-Au contact is the best solution for flip-chip bonding.

本研究针对下一代移动的终端，针对RF-CMOS系统单芯片（SOC），探讨以矽CMOS为基础的混合讯号系统LSI。研究了低功耗FFT电路、SAW器件、RF CMOS电路和低功耗数字大规模集成电路等基本器件。特别是在硅RF CMOS功率放大器、全数字单片调制解调器和3D系统芯片封装技术方面取得了显著成果。我们提出并证实了硅射频CMOS功率放大器工作在B类推挽结构和n/p-MOSFET的优化设计。功率效率大于50%，ACPR小于-33dBc，已与W-CDMA匹配。实现了面积为150 × 150 μ m^2的全数字单片调制解调器。分频数字钟已用于射频载波。从理论值与1 dB的退化传输性能已被测量使用Si LSI，这已被制造使用0.25 μ m Si工艺。提出了三维封装的新概念和带延时限制的垂直总线控制方法。接触强度使用倒装芯片键合作为一个基本的倒装芯片安装技术进行了评估。我们已经实验证实，金-金接触是倒装芯片键合的最佳解决方案。