Aconstruction of a routing synthesis system for VLSI packages

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The purpose of this research is to construct a practical automated routing synthesis system for BGA packages. In our BGA model, there are two routing layers, single chip which is smaller than package size is put on layer-one, bonding fingers are placed on the perimeter of a rectangle enclosing the chip on layer-one, solder balls are placed in a grid array pattern on layer-two, the connection requirement is given as two terminal nets that connect a bonding finger and a solder ball, and it is realized by using wires on layer-one and layer-two and vias that connect them. Further, in order to enable electric plating that improves reliability without increasing fabrication cost much, a extra wire, called plating lead, is added to each net. A plating lead connects the wire of a net to the metal ring that surrounds the package. In our conventional systems, routing patterns in which wires on layer-one are monotonic and which plating leads are on layer-one are explored, and improved by modifying via assignment iteratively. However, designers are not necessarily satisfied with the obtained routing patterns since the routing on layer-two is not necessarily completed and the several congestion errors are sometimes caused by obstacles in routing region. In this research, we enhanced our conventional systems so that the routability on layer-two is guaranteed by generating routing on layer-two by using a routing graph. Also, our system takes the obstacles into account, adopts new type of via assignment modifications that effectively reduce the routing congestion, improves the layer assignment of plating leads to utilize routing resources in layer-two efficiently, and handles plating leads of power nets. As the result, the system performance is improved and the evaluation of routing pattern obtained by the system is improved. Our system generates routing patterns equivalent to patterns obtained by designers within several seconds to several minutes.