Dependable VLSI design methodology which conquers engineering limits due to shrinking device size

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It has been recognized that a lot of problems like leakage current, delay variations, and soft-error become more serious due to shrinking device size in VLSI. In this research, we have developed an asynchronous design methodology which can tolerate any timing-related problems using the energy-efficient coding and the multi-threshold-voltage transistors. We have also developed a processor-level fault tolerance technique for dependable chip multiprocessors which will be widely used in the future technology.