权益分类	功能权益	普通用户	{{item.name}}会员
{{category.name}}	{{benefitItem.name}}

Ultra High-Performance Architecture for Real-Time Processing

用于实时处理的超高性能架构

基本信息

批准号：
12044206
负责人：
NANYA Takashi
金额：
$ 62.34万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research on Priority Areas
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2002
项目状态：
已结题

项目摘要

In this research, we proposed a cascaded ALU architecture for high-performance and real-time processing. Conventional high-performance superscalar processors suffer from increasing wire delays brought by semiconductor progress because their performance is limited by wire delay in the critical path. The Cascade ALU architecture, in which ALUs are cascaded dynamically to solve RAW dependencies between instructions, solves this problem by making the ALU part critical path. Because ALU speed is not limited by wire delays, the architecture can enjoy any further progress in device speed for an enhancement in processor performance. We have evaluated the performance and area size of the proposed cascade ALU. The results show that the cascade ALU architecture has a good performance scalability and little area penalty compared with current synchronous processors.Since the delay of the Cascade ALU varies depending on executed instructions, asynchronous circuits are suitable for its implementation … More . Thus, we developed a CAD system for asynchronous VLSIs. This system, called AlNOS, accepts ordinary synchronous RTL descriptions in Verilog-HDL and generates asynchronous gate-level circuits based on SDI model. SDI is our novel delay model which assumes that the delay scaling variation between any two components is bounded. In the SDI model based design, high-speed operation can be achieved by utilizing delay information while preserving the robustness of circuits.We also proposed a new memory architecture dedicated for high-performance and real-time processing. The memory architecture adopts software controlled memory (SCM) on the processor chip in addition to ordinary cache memory. The SCM and cache can be reconfigured dynamically depending on the characteristics of running applications. Since software can directly specify the data transfer between off-chip memory and SCM, the worst-case performance is strictly guaranteed which is favorable for real-time processing. In order to realize automatic software control, a compilation algorithm is developed and implemented. Less

在本研究中，我们提出一个高效能及即时处理的级联运算器架构。传统的高性能超标量处理器由于其性能受到关键路径线延迟的限制，而受到半导体进步带来的线延迟增加的困扰。Cascade ALU架构通过将ALU部分做成关键路径，解决了这一问题。由于ALU速度不受线延迟的限制，该体系结构可以享受设备速度的任何进一步进步以增强处理器性能。我们已经评估了建议的级联ALU的性能和面积大小。结果表明，与现有的同步处理器相比，级联ALU结构具有良好的性能可扩展性和较小的面积代价，由于级联ALU的延迟随执行指令的不同而不同，因此适合采用异步电路实现 ...更多信息 .因此，我们开发了一个异步超大规模集成电路的CAD系统。该系统采用Verilog-HDL语言的同步RTL描述，生成基于SDI模型的异步门级电路。SDI是我们的新延迟模型，它假设任何两个组件之间的延迟缩放变化是有界的。在SDI模型的基础上，设计可以实现高速操作，通过利用延迟信息，同时保持电路的鲁棒性。我们还提出了一种新的存储器结构，专用于高性能和实时处理。存储器结构除采用普通的高速缓冲存储器外，还采用了处理器芯片上的软件控制存储器（SCM）。SCM和缓存可以根据运行应用程序的特性动态重新配置。由于软件可以直接指定片外存储器与单片机之间的数据传输，因此严格保证了最坏情况下的性能，有利于实时处理。为了实现软件控制的自动化，开发并实现了编译算法。少