Ultra High-Performance Architecture for Real-Time Processing

在本研究中，我们提出了一种用于高性能和实时处理的级联ALU架构。传统的高性能超标量处理器由于其性能受到关键路径上线延迟的限制，因而受到半导体技术进步带来的线延迟增加的困扰。级联ALU架构通过动态级联ALU来解决指令之间的RAW依赖关系，通过使ALU部分成为关键路径来解决这个问题。由于ALU速度不受线路延迟的限制，因此该体系结构可以享受设备速度的任何进一步进步，以增强处理器性能。我们已经评估了所提出的级联ALU的性能和面积大小。结果表明，与现有的同步处理器相比，级联ALU架构具有良好的性能可扩展性和较小的面积损失。由于级联ALU的延迟取决于所执行的指令，因此异步电路适合其实现。因此，我们开发了一个异步超大规模集成电路的CAD系统。该系统接受Verilog-HDL中普通的同步RTL描述，并基于SDI模型生成异步门级电路，称为AlNOS。SDI是一种新的延迟模型，它假设任意两个分量之间的延迟缩放变化是有界的。在基于SDI模型的设计中，在保持电路鲁棒性的同时，利用延迟信息可以实现高速运行。我们还提出了一种新的内存架构，专门用于高性能和实时处理。该存储器结构除采用普通的高速缓存外，还在处理器芯片上采用了软件控制存储器（SCM）。SCM和缓存可以根据正在运行的应用程序的特征动态地重新配置。由于软件可以直接指定片外存储器与单片机之间的数据传输，因此严格保证了最坏情况下的性能，有利于实时处理。为了实现软件的自动控制，开发并实现了一种编译算法。少

In this research, we proposed a cascaded ALU architecture for high-performance and real-time processing. Conventional high-performance superscalar processors suffer from increasing wire delays brought by semiconductor progress because their performance is limited by wire delay in the critical path. The Cascade ALU architecture, in which ALUs are cascaded dynamically to solve RAW dependencies between instructions, solves this problem by making the ALU part critical path. Because ALU speed is not limited by wire delays, the architecture can enjoy any further progress in device speed for an enhancement in processor performance. We have evaluated the performance and area size of the proposed cascade ALU. The results show that the cascade ALU architecture has a good performance scalability and little area penalty compared with current synchronous processors.Since the delay of the Cascade ALU varies depending on executed instructions, asynchronous circuits are suitable for its implementation … More . Thus, we developed a CAD system for asynchronous VLSIs. This system, called AlNOS, accepts ordinary synchronous RTL descriptions in Verilog-HDL and generates asynchronous gate-level circuits based on SDI model. SDI is our novel delay model which assumes that the delay scaling variation between any two components is bounded. In the SDI model based design, high-speed operation can be achieved by utilizing delay information while preserving the robustness of circuits.We also proposed a new memory architecture dedicated for high-performance and real-time processing. The memory architecture adopts software controlled memory (SCM) on the processor chip in addition to ordinary cache memory. The SCM and cache can be reconfigured dynamically depending on the characteristics of running applications. Since software can directly specify the data transfer between off-chip memory and SCM, the worst-case performance is strictly guaranteed which is favorable for real-time processing. In order to realize automatic software control, a compilation algorithm is developed and implemented. Less