Study on Asynchronous VLSI System Design Methodology

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We established a design methodology to support the synthesis of high-performance and large-scale asynchronous systems. The main results of this research project are described below.(1) The speed-performance and power consumption of the asynchronous, processor TITAC-2 was evaluated. Based on the evaluation results, we defined a design strategy that speeds up an asynchronous pipeline and improves the power-performance ratio.(2) We did the RTL design of the asynchronous superscalar processor TITAC-3 in order to develop, and evaluate the defined asynchronous systems design methodology. The "cascade ALU" method, which provides a higher parallelism in instruction execution than traditional superscalar synchronous processors, was defined and adopted in TITAC-3 design. Our simulation results indicate that TITAC-3 can achieve IPC=1.90 and 258MIPS of performance.(3) The fine-grain-pipelining method was proposed, implemented and evaluated. This method takes advantage of the unique characteristics … More of DCVSL (Differential Cascode Voltage Switch Logic) circuits in order to conceal the idle-phase and controller delays. The implementation of high-speed arithmetic circuits was clarified. We proposed, implemented, and evaluated a method that adds completion-signal generation circuit to arithmetic circuits based on the SDI model.(4) We proposed and evaluated a method that synthesizes high-speed controllers from STG (Signal Transition Graph) by adding appropriate ordering relation to the graph in order to solve CSC, conflict (Complete-State-Coding conflict). Also, a method to synthesize high-speed controllers by adding ordering relations, which are based on the delay properties of the controlled data path circuit, to an STG was proposed and evaluated.(5) An online test technique using BICS (Built-In Current Sensor) that reduces the influence of premature completion signals (a peculiar problem of asynchronous circuits) was proposed.(6) A technique to realize pulse logic (which uses signal pulses as an information carrier) asynchronous data path circuits was proposed. Less