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Study on Asynchronous VLSI System Design Methodology

异步VLSI系统设计方法研究

基本信息

批准号：
09480049
负责人：
NANYA Takashi
金额：
$ 7.94万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
1997
资助国家：
日本
起止时间：
1997 至 1999
项目状态：
已结题

项目摘要

We established a design methodology to support the synthesis of high-performance and large-scale asynchronous systems. The main results of this research project are described below.(1) The speed-performance and power consumption of the asynchronous, processor TITAC-2 was evaluated. Based on the evaluation results, we defined a design strategy that speeds up an asynchronous pipeline and improves the power-performance ratio.(2) We did the RTL design of the asynchronous superscalar processor TITAC-3 in order to develop, and evaluate the defined asynchronous systems design methodology. The "cascade ALU" method, which provides a higher parallelism in instruction execution than traditional superscalar synchronous processors, was defined and adopted in TITAC-3 design. Our simulation results indicate that TITAC-3 can achieve IPC=1.90 and 258MIPS of performance.(3) The fine-grain-pipelining method was proposed, implemented and evaluated. This method takes advantage of the unique characteristics … More of DCVSL (Differential Cascode Voltage Switch Logic) circuits in order to conceal the idle-phase and controller delays. The implementation of high-speed arithmetic circuits was clarified. We proposed, implemented, and evaluated a method that adds completion-signal generation circuit to arithmetic circuits based on the SDI model.(4) We proposed and evaluated a method that synthesizes high-speed controllers from STG (Signal Transition Graph) by adding appropriate ordering relation to the graph in order to solve CSC, conflict (Complete-State-Coding conflict). Also, a method to synthesize high-speed controllers by adding ordering relations, which are based on the delay properties of the controlled data path circuit, to an STG was proposed and evaluated.(5) An online test technique using BICS (Built-In Current Sensor) that reduces the influence of premature completion signals (a peculiar problem of asynchronous circuits) was proposed.(6) A technique to realize pulse logic (which uses signal pulses as an information carrier) asynchronous data path circuits was proposed. Less

我们建立了一个设计方法，以支持高性能和大规模的异步系统的综合。该研究项目的主要成果如下。(1)异步处理器TITAC-2的速度性能和功耗进行了评估。基于评估结果，我们定义了一个设计策略，加快了异步流水线，提高了功率性能比。(2)我们做了异步超标量处理器TITAC-3的RTL设计，以开发和评估定义的异步系统设计方法。TITAC-3设计中采用了“级联ALU”方法，该方法提供了比传统超标量同步处理器更高的指令执行并行性。仿真结果表明，TITAC-3可以达到IPC=1.90和258 MIPS的性能。(3)提出了细粒度流水线方法，并进行了实现和评价。这种方法利用了 ...更多信息 DCVSL（差分共源共栅电压开关逻辑）电路，以隐藏空闲相位和控制器延迟。阐明了高速运算电路的实现。提出了一种在SDI模型基础上增加完成信号产生电路的方法。(4)我们提出并评估了一种方法，综合高速控制器从STG（信号转换图），通过添加适当的排序关系的图形，以解决CSC，冲突（完全状态编码冲突）。此外，一种方法来合成高速控制器，通过添加排序关系，这是基于受控数据路径电路的延迟特性，STG的提出和评估。(5)提出了一种利用内置电流传感器（BICS）的在线测试技术，以减少过早完成信号（异步电路特有的问题）的影响。(6)提出了一种以信号脉冲为信息载体的脉冲逻辑异步数据通路电路的实现技术。少