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Architecture and Design Method for High-Quality Hetero-Timing VLSI Systems

高质量异定时VLSI系统的架构和设计方法

基本信息

批准号：
17300013
负责人：
NANYA Takashi
金额：
$ 9.6万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2005
资助国家：
日本
起止时间：
2005 至 2006
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-17300013/
关键词：
Hetero-Timing VLSI Multi-Processor SoC Task Scheduling Low Power Consumption Delay Variation Asynchronous System SDI Model 1-out-of-4 Coding ヘテロタイミング VLSIシステム情報システムディペンダブルシステム

项目摘要

In this research, we have shown that a pipeline scheduling method is effective to reduce energy consumption for applications which are iterative and have both latency and throughput constraints. Then, we have proposed a new scheduling method based on the simulated annealing for solving the energy optimization problem. We have shown some evaluation results of throughput, latency, and energy consumption for the traditional on-chip interconnect designs based on both a synchronous scheme and an asynchronous scheme. Then, we have proposed a new interconnect circuit which can work as both a synchronous repeater circuit and an asynchronous pipeline circuit. It can change dynamically in accordance with the requirement of processing applications.We have proposed variation-aware delay cell libraries which consist of delay cells exhibiting a wide variety of delay variation characteristics considering the differences of the delay variations between PMOS transistors and NMOS transistors based on the Scalable-Delay-Insensitive model. The performance overhead can be reduced more than 30 percents compared to conventional bundled-data transfer circuits using these delay cell libraries. Then, we have focused on functional units in which a significant number of input bits may not change from the previous input in many cases. We have proposed a design method of asynchronous dual-rail circuits without redundant transitions in order to reduce energy consumption. We have also proposed a design method using the 1-out-of-4 encoding method to design low-power combinational circuits and latches. We have compared the proposed 1-out-of-4 encoded circuits with synchronous circuits in the future process technologies. It can be concluded that the 1-out-of-4 encoding method is an effective implementation to design high-performance low-power circuits in the future processes.

在这项研究中，我们已经表明，流水线调度方法是有效的，以减少能源消耗的应用程序是迭代的，有延迟和吞吐量的限制。然后，我们提出了一种新的调度方法的基础上模拟退火解决能源优化问题。我们已经展示了一些基于同步方案和异步方案的传统片上互连设计的吞吐量、延迟和能耗的评估结果。然后，我们提出了一种新的互连电路，它可以作为一个同步中继电路和异步流水线电路。我们提出了可变感知延迟单元库，该延迟单元库基于Scalable-Delay-Insensitive模型，考虑到PMOS晶体管和NMOS晶体管之间延迟变化的差异，由具有各种延迟变化特性的延迟单元组成。与传统的串行数据传输电路相比，使用这些延迟单元库的性能开销可以减少30倍以上。然后，我们重点讨论了功能单元，其中在许多情况下，大量的输入位可能不会从先前的输入中改变。提出了一种无冗余跳变的异步双轨电路设计方法，以降低功耗。我们还提出了一种使用1-out-4编码方法来设计低功耗组合电路和锁存器的设计方法。我们比较了所提出的四选一编码电路与未来工艺技术中的同步电路。可以得出结论，1-out-of-4编码方法是一个有效的实现，以设计高性能低功耗电路在未来的进程。