Architecture and Design Method for High-Quality Hetero-Timing VLSI Systems

在本研究中，我们证明了管道调度方法可以有效地降低具有延迟和吞吐量约束的迭代应用程序的能耗。然后，我们提出了一种新的基于模拟退火的调度方法来解决能量优化问题。我们展示了基于同步方案和异步方案的传统片上互连设计的吞吐量、延迟和能耗的一些评估结果。然后，我们提出了一种既可以作为同步中继电路又可以作为异步管道电路的互连电路。它可以根据处理应用的需求动态变化。考虑到PMOS晶体管和NMOS晶体管之间延迟变化的差异，我们提出了基于可缩放延迟不敏感模型的变化感知延迟单元库，该延迟单元库由具有多种延迟变化特征的延迟单元组成。与使用这些延迟单元库的传统捆绑数据传输电路相比，性能开销可以降低30%以上。然后，我们将重点放在功能单元上，其中在许多情况下，大量输入比特可能不会与之前的输入发生变化。为了降低能耗，我们提出了一种无冗余转换的异步双轨电路设计方法。我们还提出了一种采用1 out- 4编码方法设计低功耗组合电路和锁存器的设计方法。我们将提出的1 / 4编码电路与未来工艺技术中的同步电路进行了比较。可以得出结论，1 / 4编码方法是未来工艺中设计高性能低功耗电路的有效实现。

In this research, we have shown that a pipeline scheduling method is effective to reduce energy consumption for applications which are iterative and have both latency and throughput constraints. Then, we have proposed a new scheduling method based on the simulated annealing for solving the energy optimization problem. We have shown some evaluation results of throughput, latency, and energy consumption for the traditional on-chip interconnect designs based on both a synchronous scheme and an asynchronous scheme. Then, we have proposed a new interconnect circuit which can work as both a synchronous repeater circuit and an asynchronous pipeline circuit. It can change dynamically in accordance with the requirement of processing applications.We have proposed variation-aware delay cell libraries which consist of delay cells exhibiting a wide variety of delay variation characteristics considering the differences of the delay variations between PMOS transistors and NMOS transistors based on the Scalable-Delay-Insensitive model. The performance overhead can be reduced more than 30 percents compared to conventional bundled-data transfer circuits using these delay cell libraries. Then, we have focused on functional units in which a significant number of input bits may not change from the previous input in many cases. We have proposed a design method of asynchronous dual-rail circuits without redundant transitions in order to reduce energy consumption. We have also proposed a design method using the 1-out-of-4 encoding method to design low-power combinational circuits and latches. We have compared the proposed 1-out-of-4 encoded circuits with synchronous circuits in the future process technologies. It can be concluded that the 1-out-of-4 encoding method is an effective implementation to design high-performance low-power circuits in the future processes.