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Study on Architecture and Design Methdology of Asynchronous Processors

异步处理器体系结构与设计方法研究

基本信息

批准号：
04452192
负责人：
NANYA Takashi
金额：
$ 4.35万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

项目摘要

1) We developed an efficient synthesis method for asynchronous control circuits based on dependency relations between atomic operations such as register transfers and arithmetic operations. In this method, a dependency graph which describes a circuit behavior is directly mapped to a description of the interconnection among primitive circuit elements.2) We designed a quasi-delay-insensitive general-purpose 8-bit microprocessor chip TITAC,and implemented it as a CMOS gate array. The TITAC project seeks to demonstrate that a design methodology is readily available for fully asynchronous VLSI systems that work in practice. Through the design and implementation of TITAC,we established a library of building blocks for the design automation of asynchronous VLSI systems.3) We analized stuck-at faults that cause illegal signal transitions in quasi-delay-insensitive ccircuits, and proposed a design for testability by enhancing the controllability and observability of signal transitions.4) We first defined the transition causality of a self-timed implementation as a set of causal relations that hold among signal transitions on the primary input, primary output and the internal gates, and proposed a new self-timed implementation of Boolean functions. The resulting circuit achieves a maximum parallelism, and consequently, has a potential of operating at a highest possible average speed on the delay-insensitive circuit-environment model.5) We developed a gate model and circuit structure for pulse-driven asynchronous circuits implemented with the use of Josephson junction devices, in which the binary information is presented by very short voltage pulses.

1)基于寄存器转移等原子操作与算术操作之间的依赖关系，提出了一种高效的异步控制电路综合方法。在该方法中，将描述电路行为的依赖图直接映射到描述基本电路元素之间的互连关系。2)设计了一种准延迟不敏感的通用8位微处理器芯片TITAC，并将其实现为一个CMOS门阵列。TITAC项目试图证明，一种设计方法可以很容易地用于实际工作的完全异步VLSI系统。通过TITAC的设计和实现，我们建立了一个用于异步VLSI系统设计自动化的构建块库。3)分析了准延迟不敏感电路中导致非法信号跃迁的顽固错误，提出了一种通过增强信号跃迁的可控性和可观测性来实现可测试性的设计。4)我们首先定义了自定时实现的跃迁因果关系，将其定义为一组存在于主输入、主输出和内部门上的信号跃迁之间的因果关系，并提出了一种新的布尔函数的自定时实现。所得到的电路实现了最大的并行度，因此，在延迟不敏感的电路环境模型上具有以可能的最高平均速度工作的潜力。5)我们提出了一种用于使用约瑟夫森结器件实现的脉冲驱动的异步电路的门模型和电路结构，其中的二进制信息是通过非常短的电压脉冲来表示的。