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Research on Automatic Synthesis of Self-Checking Processors.

自检处理器自动综合研究。

基本信息

批准号：
02452156
负责人：
NANYA Takashi
金额：
$ 3.84万
依托单位：
Tokyo Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1990
资助国家：
日本
起止时间：
1990 至 1991
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-02452156/
关键词：
Fault-tolerance Self-checking Processor Organization Logic Circuits Logic Synthesis 論理式除算

项目摘要

Self-checking circuit design has been widely recognized as an essential technique for concurrent error detection in fault-tolerant systems. Important concepts which have been well established include : totally selfchecking(TSC)circuits which are defined to be both fault-secure(FS)and self-testing(ST), strongly faultsecure(SFS)circuits, code-disjoint(CD)circuits which include checkers as a special class, and strongly codedisjoint(SCD)circuits. SFS circuits achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. SCD circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults remain undetectable. Thus, the circuit structure which consists of an SFS functional circuit with its output monitored by an SCD checker effectively provides the largest class of self-checking circuits that achieve the TSC goal. Two or more functional circuits may be interconnected to compose a larger logic network. If a c … More omponent functional circuit embedded in the network is not only SFS but also SCD, the input of the component circuit need not be monitored by an SCD checker in order for the entire logic network to achieve the TSC goal. In this research, two important design techniques have been established for the realization of a large logic network that effectively achieves the TSC goal. First, a systematic design method is presented for SFS and SCD sequential circuits with the intensive use of highly structured logic arrays. Second, a remapping technique is presented for embedded logic functions of both combinational and sequential circuits which are interconnected with each other to compose a larger logic network. The proposed technique allows the embedded input interface of each component functional circuits to be fully exercised in normal operation so that the entire logic network proves to be SFS and SCD. Based on these design techniques, a prototype system of an automatic synthesizer for self-checking logic networks has been implemented, and shown to be useful for the automatic synthesis of self-checking processors. Less

自检电路设计已被广泛认为是容错系统中并发错误检测的一项基本技术。已有的重要概念包括：定义为故障安全(FS)和自测试(ST)的完全自检(TSC)电路、强故障安全(SFS)电路、包括作为特殊类的检验器的码不相交(CD)电路和强码不相交(SCD)电路。SFS电路实现了产生非码字作为由于故障导致的第一个错误输出的TSC目标。SCD电路始终将非码字输入映射到非码字输出，即使在存在故障的情况下，只要故障仍然不可检测。因此，由由SCD校验器监视其输出的SFS功能电路组成的电路结构有效地提供了实现TSC目标的最大类自检电路。两个或更多个功能电路可以互连以组成更大的逻辑网络。如果a c…网络中嵌入的功能电路不仅是SFS，而且是SCD，元件电路的输入不需要SCD检查器来监控，整个逻辑网络就可以实现TSC的目标。在这项研究中，为有效实现TSC目标的大型逻辑网络的实现建立了两项重要的设计技术。首先，提出了一种密集使用高结构逻辑阵列的SFS和SCD时序电路的系统设计方法。其次，针对互连的组合电路和时序电路的嵌入式逻辑功能提出了一种重映射技术，以组成更大的逻辑网络。该技术使得各部件功能电路的嵌入式输入接口在正常工作时得到充分发挥，从而使整个逻辑网络证明是SFS和SCD。基于这些设计技术，实现了一个自检逻辑网络自动综合器的原型系统，该系统对自检处理机的自动综合具有一定的实用价值。较少