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Design Methodology for Advanced VLSI Systems with Heterogeneous Timing

具有异构时序的高级 VLSI 系统的设计方法

基本信息

批准号：
13480076
负责人：
NANYA Takashi
金额：
$ 11.01万
依托单位：
The University of Tokyo
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2002
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-13480076/
关键词：
Locally timed VLSI CAD AINOS SDl model Verilog RTL Asynchronous Circuit DI Interface 2線2相式データ転送暗号化回路同期・非同期融合型VLSIシステム CAD 事象駆動原理非同期式ライブラリ STG ダブルバッファDDL メモリアーキテクチャ

项目摘要

In this work, we proposed a design method for locally timed VLSI systems in terms of a scalable delay insensitive (SDI) model. In the SDI model, although unbounded gate and wire delays are assumed, the relative delay information among gates and wires is obtained. Therefore, by using such an information, area and performance optimum VLSI systems can be designed. In addition, we developed the CAD system named AINOS and the design library to facilitate out proposed design method. In AINOS, a Verilog RTL description is accepted as the input and corresponding asynchronous system is synthesized. During the synthesis, pairs of handshake signals to realize asynchronous communication are inserted, circuits to control handshake signals are generated, and the timing verification for handshake signals is realized. Since AINOS accepts the same description used in commonly used synchronous system designs, one can design locally timed systems easily if he is familiar with the Verilog description.Together with AINOS development, we proposed several methods for the logic synthesis of locally timed VLSI systems. At first, to solve the wire delay problem, we proposed a design method so that the interface of circuits is insensitive to wire delays. As a result, the circuit can correctly operate under arbitrary wire delay for input wires. Next, to optimize asynchronous control circuits, we extended a boolean optimization method named transduction method to apply it for asynchronous control circuits. At last, we proposed a design method of control circuits to control data-path circuits with variable delay arithmetic units.

在这项工作中，我们提出了一种基于可扩展延迟不敏感（SDI）模型的局部定时VLSI系统设计方法。在SDI模型中，虽然假设门与线的延迟是无界的，但得到了门与线之间的相对延迟信息。因此，利用这些信息，可以设计出面积和性能最优的VLSI系统。此外，我们还开发了CAD系统AINOS和设计库，以方便我们提出的设计方法。在AINOS中，接受Verilog RTL描述作为输入，并合成相应的异步系统。在合成过程中，插入了实现异步通信的握手信号对，生成了握手信号控制电路，实现了握手信号的时序验证。由于AINOS接受与常用同步系统设计相同的描述，因此如果熟悉Verilog描述，就可以轻松地设计局部定时系统。结合AINOS的开发，我们提出了几种局部定时VLSI系统的逻辑综合方法。首先，为了解决线延迟问题，我们提出了一种电路接口对线延迟不敏感的设计方法。因此，该电路可以在任意输入线延迟下正确工作。其次，为了优化异步控制电路，我们扩展了一种布尔优化方法，称为转导法，将其应用于异步控制电路。最后，我们提出了一种控制电路的设计方法来控制具有可变延迟算术单元的数据路径电路。