Study on Advanced Environment for VLSI System Design Education in Universities

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With the aim of establishing a VLSI chip implementation service which supports an advanced environment of VLSI system disign education and research in Japanese universities, we conducted a pilot project to simulate multi-project-chip design and fabrication service system in order to identify any technical and economical problems encountered by the users of this system and chip foundries. In the pilot project, NTT Electronics Technology, Inc.has undertaken to play the role of the chip foundry and the multiproject chip broker.In 1994, eight universities submitted LSI design data in Verilog netlist description to NEL to implement them with a 0.5 micron CMOS gate array technology.In 1995,14 research groups from 11 universities submitted full custom designs in the stream data format to implement them as a single multi-project chip with a 0.8 microm analog CMOS technology. Another fabrication experiment with the gate array implementation was also done under the same condition as the 1994 experiment.Many problems which must be solved were indentified during the design and fabrication process for both the gate array implementation and the full custom LSI implementation. The issues which have been recognized to require further discussions towards the realization of an advanced environment for VLSI design education include ; cooperation with CAD vendors, maintenance of CAD tools, cooperation with foundries, technology update, design library, network environment, education program, staff training, publicity, and others.