Study on memory characteristics of non-volatile ferroelectric-gate transistors for neural network applications

用于神经网络应用的非易失性铁电栅晶体管的存储特性研究

• 批准号: 09450123
• 负责人: TOKUMITSU Eisuke
• 金额: $ 5.7万
• 依托单位: TOKYO INSTITUTE OF TECHNOLOGY
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (B)
• 财政年份: 1997
• 资助国家: 日本
• 起止时间: 1997 至 1998
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-09450123/
• 关键词: ferroelectrics; non-volatile memory; neural network; ferroelectric-gate transistor

The objective of this research project is to realize "learning" and "memory" functions, which are basic properties of neurons in human brains, by using silicon integrated circuits technology, In the first year (1997), we fabricated ferroelectric-gate field effect transistors (FETs) using ferroelectric SrBi_2Ta_2O_9 (SBT) film and demonstrated non-volatile memory function of the device, However, it was also found that the memory retention time was as short as 1 hour. Hence, in 1998, we analyzed the memory retention characteristics of the ferroelectric-gate FETs and showed that such short retention time was caused by mainly two reasons ; one is that depolarization field was applied during the retention time, and the second is that the operation point is on a minor loop of P-E characteristics of the ferroelectric film. To improve the retention characteristics, we fabricated metal-ferroelectric-metal-insulator-semiconductor (MFMIS) FETs. By using a small MFM capacitor on a large MIS structure, we found that the retention time was drastically improved up to more than 1 day. Next, we fabricated synaptic device which is a ferroelectric-gate FET matrix. It was demonstrated that the weighted sum operation, which is commonly used in neural networks, can be performed by the ferroelectric-gate FET matrix. Finally, we fabricated the neuron integrated circuits on SOT substrates using a ferroelectric FET with a uni-junction transistor, or CMOS Shmit-trigger pulse oscillation circuit. We have succeeded to demonstrate the learning function of the fabricated neuron circuit.

该研究项目的目的是通过使用硅综合电路技术实现“学习”和“记忆”功能，它们是人类大脑中神经元的基本特性，在第一年（1997年），我们制造了铁电挡板现场效应晶体管晶体管（FETS（FETS）发现记忆保留时间短达1小时。因此，在1998年，我们分析了铁电栅极FET的记忆保留特性，并表明如此短的保留时间主要是由两个原因引起的。一个是在保留时间内应用了去极化场，第二个是操作点是在铁电膜的P-E特性的小环上。为了提高保留特性，我们制造了金属 - 有线 - 金属 - 胰蛋白酶 - 气门导体（MFMIS）FET。通过在较大的MIS结构上使用小型MFM电容器，我们发现保留时间大大改善了至1天以上。接下来，我们制造的突触设备是铁电栅FET矩阵。已经证明，通常在神经网络中使用的加权总和可以通过铁电栅极FET矩阵进行。最后，我们使用具有单连接晶体管或CMOS SHMIT-SHMIT-TRIGGER脉冲振荡电路的铁电FET在SOT底物上制造了神经元的集成电路。我们成功地展示了制造神经元电路的学习功能。

项目成果

Byung-Eun Park: "Fabrication of PbZr_xTi_<1-x>O_3 Films on Si Structures Using Y_2O_3 Buffer Layers" Jpn.J.Appl.Phys.37-1・9B. 5145-5148 (1998)

Byung-Eun Park：“使用 Y_2O_3 缓冲层在 Si 结构上制备 PbZr_xTi_<1-x>O_3 薄膜”Jpn.J.Appl.Phys.37-1・9B (1998)。

Eisuke Tokumitsu: "Electrical Properties of MFS-FETs Using SrBi_2Ta_2O_9 Films directly Grown on Si Substrates by Sol-Gel Method" Mat.Res.Soc.Symp.Proc.493. 459-464 (1998)

Eisuke Tokumitsu：“通过溶胶-凝胶法直接在 Si 基板上生长的 SrBi_2Ta_2O_9 薄膜的 MFS-FET 的电性能”Mat.Res.Soc.Symp.Proc.493。

E.Tokumitsu, G.Fujii, and H.Ishiwara: "Electrical Properties of MFS-FETs Using SrBi_2Ta_2O_9 Films directly Grown on Si Substrates by Sol1-Gel Method" Mat.Res.Soc.Symp.Proc.493. 459-464 (1998)

E.Tokumitsu、G.Fujii 和 H.Ishiwara：“通过 Sol1-Gel 方法直接在 Si 衬底上生长的 SrBi_2Ta_2O_9 薄膜的 MFS-FET 的电性能”Mat.Res.Soc.Symp.Proc.493。

Eisuke Tokumitsu: "Nonvolatile Memory Operations of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) FET's Using PLZT/STO/Si(100)Structures" IEEE Electron Device Letters. 18・4. 160-162 (1997)

Eisuke Tokumitsu：“使用 PLZT/STO/Si(100) 结构的金属铁电绝缘体半导体 (MFIS) FET 的非易失性存储器操作”IEEE 电子器件快报 18・4 (1997)。

S.M.Yoon, E.Tokumitsu, and H.Ishiwara: "Adaptrive-Learning Neuron Integrated Circuits Using Metal-Ferroelectric (SrBi_2Ta_2O_9) -Semiconductor(MFS)FETs" IEEE Electron Device Letters. 20-5 (to be published). (1998)

S.M.Yoon、E.Tokumitsu 和 H.Ishiwara：“使用金属铁电 (SrBi_2Ta_2O_9) - 半导体 (MFS)FET 的自适应学习神经元集成电路”IEEE 电子器件通讯。